Adaptive Interval Segmentation: An Algorithmic Approach for Optimal SORN Datatypes

Fused Three-Input SORN Arithmetic

Hybrid SORN Hardware Accelerator for Support Vector Machines

On the Implementation of Edge Detection Algorithms with SORN Arithmetic

Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs

International Journal of Electronics

Two advanced energy-back SAR ADC architectures with 99.21 and 99.37 % reduction in switching energy

Analog Integrated Circuits and Signal Processing

Two-step reset method for energy-efficient SAR ADC switching schemes

Electronics Letters

Parameter identification for behavioral modeling of analog components including degradation

Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016

8 Channel neural stimulation ASIC for epidural visual cortex stimulation with on board 90 ppm/°C current reference

Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016

Compression and reconstruction methodology for neural signals based on patch ordering inpainting for brain monitoring

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Stochastic LUT-based reliability-aware design method for operation point dependent CMOS circuits

Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016

Charge-based stochastic aging analysis of CMOS circuits

IEEE International Integrated Reliability Workshop Final Report

Hardware-accelerated reconstruction of compressed neural signals based on inpainting

Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016

Bit-Error-Rate measurement of infrared physical channel using reflection via Multi Layer Insulation inside in ARIANE 5 Vehicle Equipment Bay for wireless sensor network communication

IEEE International Conference on Wireless for Space and Extreme Environments, WiSEE 2015

Degradation and temperature analysis of voltage-controlled ring oscillators for robust and reliable oscillator designs in a 65nm bulk CMOS process

Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016

Reliability-aware design method for CMOS circuits

CEUR Workshop Proceedings

A novel HV-switch scheme with gate-source overvoltage protection for bidirectional neural interfaces

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

QR-decomposition architecture based on two-variable numeric function approximation

Proceedings -Design, Automation and Test in Europe, DATE

Process variability monitor for embedded MEMS inertial sensors exploiting digital calibration coefficients

Procedia Engineering

A new current stimulator architecture for visual cortex stimulation

2015 Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP and International Symposium on System-on-Chip, SoC 2015

ADC topology based on compressed sensing for low power brain monitoring

Procedia Engineering

Design method for multiplier-less two-variable numeric function approximation

Proceedings -Design, Automation and Test in Europe, DATE

Optimum operating points of transistors with minimal aging-Aware sensitivity

Proceedings, SBCCI 2015 - 28th Symposium on Integrated Circuits and Systems Design: Chip in Bahia

NBTI and HCD aware behavioral models for reliability analysis of analog CMOS circuits

IEEE International Reliability Physics Symposium Proceedings

Variability-aware aging modeling for reliability analysis of an analog neural measurement system

Proceedings - 2015 20th IEEE European Test Symposium, ETS 2014