Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

2018 // Conference paper

Reliability Improvements for Multiprocessor Systems Through Health-Aware Task Scheduling

2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018

Schmidt, R.; Massoud, R.; Raik, J.; García-Ortiz, A.; Drechsler, R.

https://doi.org/10.1109/IOLTS.2018.8474101

2018 // Conference paper

Resilience Evaluation via Symbolic Fault Injection on Intermediate Code

Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2018

Le, H.M.; Herdt, V.; Große, D.; Drechsler, R.

https://doi.org/10.23919/DATE.2018.8342123

2018 // Conference paper

Revealing the Properties of Structural Materials by Combining Regression-Based Algorithms and Nanoindentation Measurements

2017 IEEE Symposium Series on Computational Intelligence, SSCI 2017 - Proceedings

Huhn, S.; Sonnenberg, H.; Eggersglus, S.; Clausen, B.; Drechsler, R.

https://doi.org/10.1109/SSCI.2017.8285180

2018 // Conference paper

SAT-Lancer: A Hardware SAT Solver for Self-Verification

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Ustaoglu, B.; Huhn, S.; Große, D.; Drechsler, R.

https://doi.org/10.1145/3194554.3194643

2018 // Journal article

Synthesis of Circuits Based on All-Optical Mach-Zehnder Interferometers Using Binary Decision Diagrams

Microelectronics Journal

Bandyopadhyay, C.; Das, R.; Wille, R.; Drechsler, R.; Rahaman, H.

https://doi.org/10.1016/j.mejo.2017.11.008

2018 // Conference paper

Synthesis of Reversible Circuits Using Conventional Hardware Description Languages

Proceedings of The International Symposium on Multiple-Valued Logic

Alwardi, Z.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2018.00025

2018 // Conference paper

Testbench Qualification for SystemC-AMS Timed Data Flow Models

Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2018

Hassan, M.; Große, D.; Le, H.M.; Vörtler, T.; Einwich, K.; Drechsler, R.

https://doi.org/10.23919/DATE.2018.8342125

2018 // Journal article

The Complexity of Error Metrics

Information Processing Letters

Keszocze, O.; Soeken, M.; Drechsler, R.

https://doi.org/10.1016/j.ipl.2018.06.010

2018 // Conference paper

Toward a Methodology for Self-Verification

2017 6th International Conference on Reliability, Infocom Technologies, and Optimization: Trends and Future Directions, ICRITO 2017

Luth, C.; Ring, M.; Drechsler, R.

https://doi.org/10.1109/ICRITO.2017.8342390

2018 // Conference paper

Toward a Dynamic Execution Environment for System Security Protection Against Hardware Flaws

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Schmitz, K.; Keszocze, O.; Schmidt, J.; Grobe, D.; Drechsler, R.

https://doi.org/10.1109/ISVLSI.2018.00107

2018 // Conference paper

Toward Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach

Forum on Specification and Design Languages

Herdt, V.; Le, H.M.; Grose, D.; Drechsler, R.

https://doi.org/10.1109/FDL.2017.8303898

2018 // Conference paper

Toward Fully Automated TLM-to-RTL Property Refinement

Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2018

Herdt, V.; Le, H.M.; Grose, D.; Drechsler, R.

https://doi.org/10.23919/DATE.2018.8342253

2018 // Conference paper

Toward Lightweight Satisfiability Solvers for Self-Verification

2017 7th International Symposium on Embedded Computing and System Design, ISED 2017

Bornebusch, F.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/ISED.2017.8303924

2018 // Conference paper

Toward Reversed Approximate Hardware Design

Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018

Froehlich, S.; Grobe, D.; Drechsler, R.

https://doi.org/10.1109/DSD.2018.00112

2018 // Conference paper

Toward Self-Explaining Digital Systems: A Design Methodology for the Next Generation

2018 IEEE 3rd International Verification and Security Workshop, IVSW 2018

Drechsler, R.; Luth, C.; Fey, G.; Guneysu, T.

https://doi.org/10.1109/IVSW.2018.8494900

2018 // Conference paper

Toward Self-Explaining Intelligent Environments

2018 7th International Conference on Reliability, Infocom Technologies, and Optimization: Trends and Future Directions, ICRITO 2018

Autexier, S.; Drechsler, R.

https://doi.org/10.1109/ICRITO.2018.8748460

2018 // Conference paper

Verifying Next-Generation Electronic Systems

2017 International Conference on Infocom Technologies and Unmanned Systems: Trends and Future Directions, ICTUS 2017

Drechsler, R.; Grose, D.

https://doi.org/10.1109/ICTUS.2017.8285965

2017 // Other

A PLiM Computer for the Internet of Things

Computer

Soeken, M.; Gaillardon, P.-E.; Shirinzadeh, S.; Drechsler, R.; De Micheli, G.

https://doi.org/10.1109/MC.2017.173

2017 // Book

Advanced logic synthesis

Advanced Logic Synthesis

Reis, A.I.; Drechsler, R.

https://doi.org/10.1007/978-3-319-67295-3

2017 // Conference paper

An Adaptive, Prioritized, ϵ-Preferred Evolutionary Algorithm for Approximate BDD Optimization

GECCO 2017 - Proceedings of the 2017 Genetic and Evolutionary Computation Conference

Shirinzadeh, S.; Soeken, M.; Große, D.; Drechsler, R.

https://doi.org/10.1145/3071178.3071281

2017 // Journal article

An Automated Approach for Generating and Verifying Control Logic for Designs Based on the Reversible Hardware Description Language

Journal of Low-Power Electronics

Wille, R.; Keszocze, O.; Othmer, L.; Thomsen, M.K.; Drechsler, R.

https://doi.org/10.1166/jolpe.2017.1515

2017 // Conference paper

An Improved Gate Library for the Logic Synthesis of Optical Circuits

Proceedings - 2016 6th International Symposium on Embedded Computing and System Design, ISED 2016

Burman, S.; Datta, K.; Wille, R.; Sengupta, I.; Drechsler, R.

https://doi.org/10.1109/ISED.2016.7977044

2017 // Conference paper

Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications

Proceedings of the 2017 Design, Automation, and Test in Europe (DATE 2017)

Goli, M.; Stoppe, J.; Drechsler, R.

https://doi.org/10.23919/DATE.2017.7927064

2017 // Conference paper

Automatic protocol compliance checking of SystemC TLM-2.0 simulation behavior using timed automata

Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017

Goli, M.; Stoppe, J.; Drechsler, R.

https://doi.org/10.1109/ICCD.2017.65

2017 // Conference paper

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Stoppe, J.; Keszöcze, O.; Luenert, M.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/ISVLSI.2017.38

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Prof. Rolf Drechsler

Ecosystem

Publications

Reliability Improvements for Multiprocessor Systems Through Health-Aware Task Scheduling

Resilience Evaluation via Symbolic Fault Injection on Intermediate Code

Revealing the Properties of Structural Materials by Combining Regression-Based Algorithms and Nanoindentation Measurements

SAT-Lancer: A Hardware SAT Solver for Self-Verification

Synthesis of Circuits Based on All-Optical Mach-Zehnder Interferometers Using Binary Decision Diagrams

Synthesis of Reversible Circuits Using Conventional Hardware Description Languages

Testbench Qualification for SystemC-AMS Timed Data Flow Models

The Complexity of Error Metrics

Toward a Methodology for Self-Verification

Toward a Dynamic Execution Environment for System Security Protection Against Hardware Flaws

Toward Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach

Toward Fully Automated TLM-to-RTL Property Refinement

Toward Lightweight Satisfiability Solvers for Self-Verification

Toward Reversed Approximate Hardware Design

Toward Self-Explaining Digital Systems: A Design Methodology for the Next Generation

Toward Self-Explaining Intelligent Environments

Verifying Next-Generation Electronic Systems

A PLiM Computer for the Internet of Things

Advanced logic synthesis

An Adaptive, Prioritized, ϵ-Preferred Evolutionary Algorithm for Approximate BDD Optimization

An Automated Approach for Generating and Verifying Control Logic for Designs Based on the Reversible Hardware Description Language

An Improved Gate Library for the Logic Synthesis of Optical Circuits

Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications

Automatic protocol compliance checking of SystemC TLM-2.0 simulation behavior using timed automata

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions