Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

2013 // Book

Using πdDs in the design of reversible circuits (work in progress)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Soeken, M.; Wille, R.; Minato, S.-I.; Drechsler, R.

https://doi.org/10.1007/978-3-642-36315-3-16

2013 // Conference paper

Verifying SystemC Using an Intermediate Verification Language and Symbolic Simulation

Proceedings - Design Automation Conference

Le, H.M.; Große, D.; Herdt, V.; Drechsler, R.

https://doi.org/10.1145/2463209.2488877

2012 // Conference paper

A guiding coverage metric for formal verification

Proceedings -Design, Automation and Test in Europe, DATE

Haedicke, F.; Große, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84862078000&partnerID=MN8TOARS

2012 // Journal article

A Highly Fault-Tolerant Satellite-Based ATPG Flow

IEEE Design and Test of Computers

Eggersglüß, S.; Drechsler, R.

https://doi.org/10.1109/MDT.2012.2205479

2012 // Conference paper

A new SAT-based ATPG for generating highly compacted test sets

Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012

Eggersglüß, S.; Krenz-Bååth, R.; Glowatz, A.; Hapke, F.; Drechsler, R.

https://doi.org/10.1109/DDECS.2012.6219063

2012 // Conference paper

A synthesis flow for sequential reversible circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Soeken, M.; Wille, R.; Otterstedt, C.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2012.72

2012 // Book

Assisted behavior-driven development using natural language processing

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Soeken, M.; Wille, R.; Drechsler, R.

https://doi.org/10.1007/978-3-642-30561-0_19

2012 // Conference paper

Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis

Proceedings -Design, Automation and Test in Europe, DATE

Wille, R.; Drechsler, R.; Osewold, C.; Garcia-Ortiz, A.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84862090064&partnerID=MN8TOARS

2012 // Journal article

Automatic TLM Fault Localization for SystemC

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Le, H.M.; Grosse, D.; Drechsler, R.

https://doi.org/10.1109/TCAD.2012.2188800

2012 // Conference paper

Behavior-Driven Development for Circuit Design and Verification

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Diepenbeck, M.; Soeken, M.; Große, D.; Drechsler, R.

https://doi.org/10.1109/HLDVT.2012.6418237

2012 // Conference paper

Circuit Line Minimization in HDL-Based Synthesis of Reversible Logic

Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Wille, R.; Soeken, M.; Schönborn, E.; Drechsler, R.

https://doi.org/10.1109/ISVLSI.2012.43

2012 // Conference paper

Complete and effective robustness checking using interpolation

2012 Formal Methods in Computer-Aided Design, FMCAD 2012

Frehse, S.; Fey, G.; Arbel, E.; Yorav, K.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84874589406&partnerID=MN8TOARS

2012 // Book

Completeness-Driven Development

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, R.; Diepenbeck, M.; Große, D.; Kühne, U.; Le, H.M.; Seiter, J.; Soeken, M.; Wille, R.

https://doi.org/10.1007/978-3-642-33654-6_3

2012 // Conference paper

CRAVE: An advanced constrained random verification environment for SystemC

2012 International Symposium on System-on-Chip, SoC 2012

Haedicke, F.; Le, H.M.; Grosse, D.; Drechsler, R.

https://doi.org/10.1109/ISSoC.2012.6376356

2012 // Conference paper

Debugging Inconsistent UML/OCL Models

Proceedings -Design, Automation and Test in Europe, DATE

Wille, R.; Soeken, M.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84862108901&partnerID=MN8TOARS

2012 // Conference paper

Eliminating invariants in UML/OCL models

Proceedings -Design, Automation and Test in Europe, DATE

Soeken, M.; Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84862090697&partnerID=MN8TOARS

2012 // Journal article

Equivalence checking of reversible circuits

Journal of Multiple-Valued Logic and Soft Computing

Wille, R.; Grosse, D.; Miller, D.M.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84866676898&partnerID=MN8TOARS

2012 // Conference paper

Exact synthesis of Toffoli gate circuits with negative control lines

Proceedings of The International Symposium on Multiple-Valued Logic

Wille, R.; Soeken, M.; Przigoda, N.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2012.71

2012 // Journal article

Foreword: Special Issue on Reversible Computation

Journal of Multiple-Valued Logic and Soft Computing

Drechsler, R.; Ulidowski, I.; Wille, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84555203344&partnerID=MN8TOARS

2012 // Conference paper

Formal Specification Level: Toward Verification-Driven Design Based on Natural Language Processing

Forum on Specification and Design Languages

Drechsler, R.; Soeken, M.; Wille, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84871088397&partnerID=MN8TOARS

2012 // Conference paper

From Requirements and Scenarios to ESL Design in SystemC

Proceedings - 2012 International Symposium on Electronic System Design, ISED 2012

Le, H.M.; Grosse, D.; Drechsler, R.

https://doi.org/10.1109/ISED.2012.36

2012 // Conference paper

Generating formal system models from natural language descriptions

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Drechsler, R.; Harris, I.G.; Wille, R.

https://doi.org/10.1109/HLDVT.2012.6418259

2012 // Book

High-quality test pattern generation and Boolean satisfiability

High-Quality Test Pattern Generation and Boolean Satisfiability

Eggersglüß, S.; Drechsler, R.

https://doi.org/10.1007/978-1-4419-9976-4

2012 // Book

Lecture Notes in Computer Science (including the subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Di Chio, C.; Agapitos, A.; Cagnoni, S.; Cotta, C.; De Vega, F.F.; Di Caro, G.; Drechsler, R.; Ekárt, A.; Esparcia-Alcázar, A.I.; Farooq, M.; Langdon, W.B.; Merelo-Guervós, J.-J.; Preuss, M.; Richter, H.; Silva, S.; Simões, A.; Squillero, G.; Tarantino, E.; Tettamanzi, A.G.B.; Togelius, J.; Urqhart, N.; Uyar, A.S.; Yannakakis, G.N.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84859303873&partnerID=MN8TOARS

2012 // Conference paper

Localizing Features of ESL Models for Design Understanding

Forum on Specification and Design Languages

Michael, M.; Große, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84871049012&partnerID=MN8TOARS

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Prof. Rolf Drechsler

Ecosystem

Publications

Using πdDs in the design of reversible circuits (work in progress)

Verifying SystemC Using an Intermediate Verification Language and Symbolic Simulation

A guiding coverage metric for formal verification

A Highly Fault-Tolerant Satellite-Based ATPG Flow

A new SAT-based ATPG for generating highly compacted test sets

A synthesis flow for sequential reversible circuits

Assisted behavior-driven development using natural language processing

Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis

Automatic TLM Fault Localization for SystemC

Behavior-Driven Development for Circuit Design and Verification

Circuit Line Minimization in HDL-Based Synthesis of Reversible Logic

Complete and effective robustness checking using interpolation

Completeness-Driven Development

CRAVE: An advanced constrained random verification environment for SystemC

Debugging Inconsistent UML/OCL Models

Eliminating invariants in UML/OCL models

Equivalence checking of reversible circuits

Exact synthesis of Toffoli gate circuits with negative control lines

Foreword: Special Issue on Reversible Computation

Formal Specification Level: Toward Verification-Driven Design Based on Natural Language Processing

From Requirements and Scenarios to ESL Design in SystemC

Generating formal system models from natural language descriptions

High-quality test pattern generation and Boolean satisfiability

Lecture Notes in Computer Science (including the subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface

Localizing Features of ESL Models for Design Understanding

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions