© Jörg Sarbach
© Jörg Sarbach
Prof. Rolf Drechsler

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Publikationen
2013 // Book

Using πdDs in the design of reversible circuits (work-in-progress)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Soeken, M.; Wille, R.; Minato, S.-I.; Drechsler, R.

2013 // Conference paper

Verifying systemC using an intermediate verification language and symbolic simulation

Proceedings - Design Automation Conference

Le, H.M.; Große, D.; Herdt, V.; Drechsler, R.

2012 // Conference paper

A guiding coverage metric for formal verification

Proceedings -Design, Automation and Test in Europe, DATE

Haedicke, F.; Große, D.; Drechsler, R.

2012 // Journal article

A highly fault-efficient sat-based atpg flow

IEEE Design and Test of Computers

Eggersglüß, S.; Drechsler, R.

2012 // Conference paper

A new SAT-based ATPG for generating highly compacted test sets

Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012

Eggersglüß, S.; Krenz-Bååth, R.; Glowatz, A.; Hapke, F.; Drechsler, R.

2012 // Conference paper

A synthesis flow for sequential reversible circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Soeken, M.; Wille, R.; Otterstedt, C.; Drechsler, R.

2012 // Book

Assisted behavior driven development using natural language processing

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Soeken, M.; Wille, R.; Drechsler, R.

2012 // Conference paper

Automatic design of low-power encoders using reversible circuit synthesis

Proceedings -Design, Automation and Test in Europe, DATE

Wille, R.; Drechsler, R.; Osewold, C.; Garcia-Ortiz, A.

2012 // Journal article

Automatic TLM fault localization for SystemC

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Le, H.M.; Grosse, D.; Drechsler, R.

2012 // Conference paper

Behavior driven development for circuit design and verification

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Diepenbeck, M.; Soeken, M.; Große, D.; Drechsler, R.

2012 // Conference paper

Circuit line minimization in the HDL-based synthesis of reversible logic

Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Wille, R.; Soeken, M.; Schönborn, E.; Drechsler, R.

2012 // Conference paper

Complete and effective robustness checking by means of interpolation

2012 Formal Methods in Computer-Aided Design, FMCAD 2012

Frehse, S.; Fey, G.; Arbel, E.; Yorav, K.; Drechsler, R.

2012 // Book

Completeness-driven development

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, R.; Diepenbeck, M.; Große, D.; Kühne, U.; Le, H.M.; Seiter, J.; Soeken, M.; Wille, R.

2012 // Conference paper

CRAVE: An advanced constrained random verification environment for SystemC

2012 International Symposium on System on Chip, SoC 2012

Haedicke, F.; Le, H.M.; Grosse, D.; Drechsler, R.

2012 // Conference paper

Debugging of inconsistent UML/OCL models

Proceedings -Design, Automation and Test in Europe, DATE

Wille, R.; Soeken, M.; Drechsler, R.

2012 // Conference paper

Eliminating invariants in UML/OCL models

Proceedings -Design, Automation and Test in Europe, DATE

Soeken, M.; Wille, R.; Drechsler, R.

2012 // Journal article

Equivalence checking of reversible circuits

Journal of Multiple-Valued Logic and Soft Computing

Wille, R.; Grosse, D.; Miller, D.M.; Drechsler, R.

2012 // Conference paper

Exact synthesis of toffoli gate circuits with negative control lines

Proceedings of The International Symposium on Multiple-Valued Logic

Wille, R.; Soeken, M.; Przigoda, N.; Drechsler, R.

2012 // Journal article

Foreword: Special issue on reversible computation

Journal of Multiple-Valued Logic and Soft Computing

Drechsler, R.; Ulidowski, I.; Wille, R.

2012 // Conference paper

Formal specification level: Towards verification-driven design based on natural language processing

Forum on Specification and Design Languages

Drechsler, R.; Soeken, M.; Wille, R.

2012 // Conference paper

From requirements and scenarios to ESL design in SystemC

Proceedings - 2012 International Symposium on Electronic System Design, ISED 2012

Le, H.M.; Grosse, D.; Drechsler, R.

2012 // Conference paper

Generating formal system models from natural language descriptions

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Drechsler, R.; Harris, I.G.; Wille, R.

2012 // Book

High quality test pattern generation and boolean satisfiability

High Quality Test Pattern Generation and Boolean Satisfiability

Eggersglüß, S.; Drechsler, R.

2012 // Book

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Di Chio, C.; Agapitos, A.; Cagnoni, S.; Cotta, C.; De Vega, F.F.; Di Caro, G.; Drechsler, R.; Ekárt, A.; Esparcia-Alcázar, A.I.; Farooq, M.; Langdon, W.B.; Merelo-Guervós, J.-J.; Preuss, M.; Richter, H.; Silva, S.; Simões, A.; Squillero, G.; Tarantino, E.; Tettamanzi, A.G.B.; Togelius, J.; Urqhart, N.; Uyar, A.S.; Yannakakis, G.N.

2012 // Conference paper

Localizing features of ESL models for design understanding

Forum on Specification and Design Languages

Michael, M.; Große, D.; Drechsler, R.