Wissenschaftsschwerpunkt der

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© Jörg Sarbach
© Jörg Sarbach
Prof. Rolf Drechsler
  • Fachbereich: Fachbereich 3 - Mathematik & Informatik
  • Fachgebiet: Computer Architecture (systems descriptions, test and verification, synthesis) Further Information: Group of Computer Architecture; Group of Reliable Embedded Systems; DFKI Cyber Physical Systems
  • Büro: MZH 4330

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Mitglied des Direktoriums des Wissenschaftsschwerpunkts "Minds, Media, Machines"
Leiter der Arbeitsgruppe Rechnerarchitektur
Direktor der Gruppe Cyber Physical Systems am Deutschen Forschungszentrum für Künstliche Intelligenz (DFKI)
Mitgründer und Sprecher des Data Science Center (DSC) an der Universität Bremen
Dekan des Fachbereichs 3 Mathematik/Informatik
Betreuer für das Graduiertenkolleg „CAUSE“
Mitglied des CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI
Mitglied des Direktoriums des Forschungscluster "Logdynamics"
Publikationen
2012 // Conference paper

Optimizing the mapping of reversible circuits to four-valued quantum gate circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Soeken, M.; Sasanian, Z.; Wille, R.; Miller, D.M.; Drechsler, R.
https://doi.org/10.1109/ISMVL.2012.64
2012 // Journal article

Reducing reversible circuit cost by adding lines

Journal of Multiple-Valued Logic and Soft Computing

Michael Miller, D.; Wille, R.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-84864054460&partnerID=MN8TOARS
2012 // Book

Reversible circuits: Recent accomplishments and future challenges for an emerging technology (Invited paper)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, R.; Wille, R.
https://doi.org/10.1007/978-3-642-31494-0_53
2012 // Journal article

Revkit: A toolkit for reversible circuit design

Journal of Multiple-Valued Logic and Soft Computing

Soeken, M.; Frehse, S.; Wille, R.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-84555205270&partnerID=MN8TOARS
2012 // Book

RevKit: An open source toolkit for the design of reversible circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Soeken, M.; Frehse, S.; Wille, R.; Drechsler, R.
https://doi.org/10.1007/978-3-642-29517-1_6
2012 // Conference paper

Synthesis of reversible circuits using decision diagrams

Proceedings - 2012 International Symposium on Electronic System Design, ISED 2012

Drechsler, R.; Wille, R.
https://doi.org/10.1109/ISED.2012.37
2012 // Conference paper

Synthesis of reversible circuits with minimal lines for large functions

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Soeken, M.; Wille, R.; Hilken, C.; Przigoda, N.; Drechsler, R.
https://doi.org/10.1109/ASPDAC.2012.6165069
2012 // Book

SyReC: A programming language for synthesis of reversible circuits

Lecture Notes in Electrical Engineering

Wille, R.; Offermann, S.; Drechsler, R.
https://doi.org/10.1007/978-1-4614-1427-8_13
2012 // Conference paper

The System Verification Methodology for advanced TLM verification

CODES+ISSS'12 - Proceedings of the 10th ACM International Conference on Hardware/Software-Codesign and System Synthesis, Co-located with ESWEEK

Oliveira, M.F.S.; Haedicke, F.; Drechsler, R.; Kuznik, C.; Le, H.M.; Ecker, W.; Mueller, W.; Große, D.; Esen, V.
https://doi.org/10.1145/2380445.2380497
2011 // Conference paper

Analyzing dependability measures at the electronic system level

Forum on Specification and Design Languages

Michael, M.; Große, D.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-82955186176&partnerID=MN8TOARS
2011 // Conference paper

As-robust-as-possible test generation in the presence of small delay defects using pseudo-Boolean optimization

Proceedings -Design, Automation and Test in Europe, DATE

Eggersglüß, S.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-79957544175&partnerID=MN8TOARS
2011 // Conference paper

ATPG for reversible circuits using simulation, Boolean satisfiability, and pseudo Boolean optimization

Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Wille, R.; Zhang, H.; Drechsler, R.
https://doi.org/10.1109/ISVLSI.2011.77
2011 // Conference paper

Automatic fault localization for Programmable Logic Controllers

FORMS/FORMAT 2010 - Formal Methods for Automation and Safety in Railway and Automotive Systems

Sülflow, A.; Drechsler, R.
https://doi.org/10.1007/978-3-642-14261-1-25
2011 // Conference paper

Automatic property generation for the formal verification of bus bridges

Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

Soeken, M.; Kühne, U.; Freibothe, M.; Fe, G.; Drechsler, R.
https://doi.org/10.1109/DDECS.2011.5783129
2011 // Journal article

Debugging reversible circuits

Integration, the VLSI Journal

Wille, R.; Große, D.; Frehse, S.; Dueck, G.W.; Drechsler, R.
https://doi.org/10.1016/j.vlsi.2010.08.002
2011 // Conference paper

Designing a RISC CPU in reversible logic

Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011

Wille, R.; Soeken, M.; Große, D.; Schönborn, E.; Drechsler, R.
https://doi.org/10.1109/ISMVL.2011.39
2011 // Conference paper

Determining minimal testsets for reversible circuits using Boolean satisfiability

IEEE AFRICON Conference

Zhang, H.; Frehse, S.; Wille, R.; Drechsler, R.
https://doi.org/10.1109/AFRCON.2011.6072128
2011 // Conference paper

Determining the minimal number of lines for large reversible circuits

Proceedings -Design, Automation and Test in Europe, DATE

Wille, R.; Keszöcze, O.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-79957555773&partnerID=MN8TOARS
2011 // Journal article

Effective robustness analysis using bounded model checking techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Fey, G.; Sulflow, A.; Frehse, S.; Drechsler, R.
https://doi.org/10.1109/TCAD.2011.2120950
2011 // Journal article

Efficient data structures and methodologies for SAT-based ATPG providing high fault coverage in industrial application

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Eggersglüß, S.; Drechsler, R.
https://doi.org/10.1109/TCAD.2011.2152450
2011 // Conference paper

Efficient realization of control logic in reversible circuits

Forum on Specification and Design Languages

Offermann, S.; Wille, R.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-82955186192&partnerID=MN8TOARS
2011 // Book

Encoding OCL data types for SAT-based verification of UML/OCL models

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Soeken, M.; Wille, R.; Drechsler, R.
https://doi.org/10.1007/978-3-642-21768-5_12
2011 // Conference paper

From truth tables to programming languages: Progress in the design of reversible circuits

Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011

Drechsler, R.; Wille, R.
https://doi.org/10.1109/ISMVL.2011.40
2011 // Conference paper

Improved fault diagnosis for reversible circuits

Proceedings of the Asian Test Symposium

Zhang, H.; Wille, R.; Drechsler, R.
https://doi.org/10.1109/ATS.2011.29
2011 // Book

Improving ESOP-based synthesis of reversible logic using evolutionary algorithms

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, R.; Finder, A.; Wille, R.
https://doi.org/10.1007/978-3-642-20520-0_16

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.

mmm@uni-bremen.de 

  • 2026 Minds, Media, Machines

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.

mmm@uni-bremen.de 

  • 2026 Minds, Media, Machines