Wissenschaftsschwerpunkt der

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© Jörg Sarbach
© Jörg Sarbach
Prof. Rolf Drechsler
  • Fachbereich: Fachbereich 3 - Mathematik & Informatik
  • Fachgebiet: Computer Architecture (systems descriptions, test and verification, synthesis) Further Information: Group of Computer Architecture; Group of Reliable Embedded Systems; DFKI Cyber Physical Systems
  • Büro: MZH 4330

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Mitglied des Direktoriums des Wissenschaftsschwerpunkts "Minds, Media, Machines"
Leiter der Arbeitsgruppe Rechnerarchitektur
Direktor der Gruppe Cyber Physical Systems am Deutschen Forschungszentrum für Künstliche Intelligenz (DFKI)
Mitgründer und Sprecher des Data Science Center (DSC) an der Universität Bremen
Dekan des Fachbereichs 3 Mathematik/Informatik
Betreuer für das Graduiertenkolleg „CAUSE“
Mitglied des CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI
Mitglied des Direktoriums des Forschungscluster "Logdynamics"
Publikationen
2011 // Conference paper

MetaSMT: Focus on your application not on solver integration

CEUR Workshop Proceedings

Haedicke, F.; Frehse, S.; Fey, G.; Große, D.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-84879877391&partnerID=MN8TOARS
2011 // Conference paper

Simulation-based equivalence checking between SystemC models at different levels of abstraction

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Große, D.; Groß, M.; Kühne, U.; Drechsler, R.
https://doi.org/10.1145/1973009.1973054
2011 // Journal article

Synthesis of quantum circuits for linear nearest neighbor architectures

Quantum Information Processing

Saeedi, M.; Wille, R.; Drechsler, R.
https://doi.org/10.1007/s11128-010-0201-2
2011 // Conference paper

TLM protocol compliance checking at the Electronic System Level

Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

Bawadekji, M.; Große, D.; Drechsler, R.
https://doi.org/10.1109/DDECS.2011.5783132
2011 // Conference paper

Towards automatic determination of problem bounds for object instantiation in static model verification

ACM International Conference Proceeding Series

Soeken, M.; Wille, R.; Drechsler, R.
https://doi.org/10.1145/2095654.2095657
2011 // Conference paper

Towards dependability-aware design of hardware systems using extended program state machines

Proceedings - 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, ISORCW 2011

Grüttner, K.; Herrholz, A.; Kühne, U.; Große, D.; Rettberg, A.; Nebel, W.; Drechsler, R.
https://doi.org/10.1109/ISORCW.2011.27
2011 // Conference paper

Verifying dynamic aspects of UML models

Proceedings -Design, Automation and Test in Europe, DATE

Soeken, M.; Wille, R.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-79957538504&partnerID=MN8TOARS
2010 // Conference paper

A better-than-worst-case robustness measure

Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Frehse, S.; Fey, G.; Drechsler, R.
https://doi.org/10.1109/DDECS.2010.5491812
2010 // Conference paper

An evolutionary algorithm for optimization of Pseudo Kronecker Expressions

Proceedings of The International Symposium on Multiple-Valued Logic

Finder, A.; Drechsler, R.
https://doi.org/10.1109/ISMVL.2010.36
2010 // Journal article

Automated Formal Verification of Fault Tolerance for Circuits,Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen

IT - Information Technology

Fey, G.; Sülflow, A.; Frehse, S.; Drechsler, R.
https://doi.org/10.1524/itit.2010.0594
2010 // Conference paper

Automatic fault localization for SystemC TLM designs

Proceedings - International Workshop on Microprocessor Test and Verification

Le, H.M.; Große, D.; Drechsler, R.
https://doi.org/10.1109/MTV.2010.15
2010 // Conference paper

Bounded fault tolerance checking

IET Seminar Digest

Sülflow, A.; Fey, G.; Drechsler, R.
https://doi.org/10.1049/ic.2010.0120
2010 // Book

Debugging at the electronic system level

Debugging at the Electronic System Level

Rogin, F.; Drechsler, R.
https://doi.org/10.1007/978-90-481-9255-7
2010 // Journal article

Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic

Electronic Notes in Theoretical Computer Science

Wille, R.; Drechsler, R.
https://doi.org/10.1016/j.entcs.2010.02.006
2010 // Conference paper

Efficient simulation-based debugging of reversible logic

Proceedings of The International Symposium on Multiple-Valued Logic

Frehse, S.; Wille, R.; Drechsler, R.
https://doi.org/10.1109/ISMVL.2010.37
2010 // Conference paper

Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Eggersglüß, S.; Tille, D.; Drechsler, R.
https://doi.org/10.1109/ISCAS.2010.5537503
2010 // Conference paper

Enhancing debugging of multiple missing control errors in reversible logic

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Jung, J.C.; Frehse, S.; Wille, R.; Drechsler, R.
https://doi.org/10.1145/1785481.1785588
2010 // Conference paper

Hierarchical synthesis of reversible circuits using positive and negative davio decomposition

IDT'10 - 2010 5th International Design and Test Workshop, Proceedings

Soeken, M.; Wille, R.; Drechsler, R.
https://doi.org/10.1109/IDT.2010.5724427
2010 // Conference paper

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs

2010 15th IEEE European Test Symposium, ETS'10

Tille, D.; Eggersglüß, S.; Krenz-Bååth, R.; Schloeffel, J.; Drechsler, R.
https://doi.org/10.1109/ETSYM.2010.5512763
2010 // Journal article

Incremental solving techniques for SAT-based ATPG

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Tille, D.; Eggersglus, S.; Drechsler, R.
https://doi.org/10.1109/TCAD.2010.2044673
2010 // Journal article

MONSOON: SAT-based ATPG for path delay faults using multiple-valued logics

Journal of Electronic Testing: Theory and Applications (JETTA)

Eggersglüß, S.; Fey, G.; Glowatz, A.; Hapke, F.; Schloeffel, J.; Drechsler, R.
https://doi.org/10.1007/s10836-010-5146-y
2010 // Conference paper

Polynomial datapath optimization using constraint solving and formal modelling

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Haedicke, F.; Alizadeh, B.; Fey, G.; Fujita, M.; Drechsler, R.
https://doi.org/10.1109/ICCAD.2010.5654279
2010 // Conference paper

Proving transaction and system-level properties of untimed SystemC TLM designs

8th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2010

Große, D.; Le, H.M.; Drechsler, R.
https://doi.org/10.1109/MEMCOD.2010.5558643
2010 // Book

Quality-driven SystemC design

Quality-Driven SystemC Design

Große, D.; Drechsler, R.
https://doi.org/10.1007/978-90-481-3631-5
2010 // Conference paper

Reducing reversible circuit cost by adding lines

Proceedings of The International Symposium on Multiple-Valued Logic

Miller, D.M.; Wille, R.; Drechsler, R.
https://doi.org/10.1109/ISMVL.2010.48

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.

mmm@uni-bremen.de 

  • 2026 Minds, Media, Machines

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.

mmm@uni-bremen.de 

  • 2026 Minds, Media, Machines