Prof. Rolf Drechsler

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Mitglied des Direktoriums des Wissenschaftsschwerpunkts "Minds, Media, Machines"

Leiter der Arbeitsgruppe Rechnerarchitektur

Direktor der Gruppe Cyber Physical Systems am Deutschen Forschungszentrum für Künstliche Intelligenz (DFKI)

Mitgründer und Sprecher des Data Science Center (DSC) an der Universität Bremen

Dekan des Fachbereichs 3 Mathematik/Informatik

Betreuer für das Graduiertenkolleg „CAUSE“

Mitglied des CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Mitglied des Direktoriums des Forschungscluster "Logdynamics"

Publikationen

2010 // Conference paper

Reducing the number of lines in reversible circuits

Proceedings - Design Automation Conference

Wille, R.; Soeken, M.; Drechsler, R.

https://doi.org/10.1145/1837274.1837439

2010 // Conference paper

RobuCheck: A robustness checker for digital circuits

ACM International Conference Proceeding Series

Frehse, S.; Fey, G.; Sülflow, A.; Drechsler, R.

https://doi.org/10.1145/1772630.1772641

2010 // Conference paper

RobuCheck: A robustness checker for digital circuits

Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010

Frehse, S.; Fey, G.; Sülflow, A.; Drechsler, R.

https://doi.org/10.1109/DSD.2010.91

2010 // Conference paper

Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability

Proceedings - International Test Conference

Eggersglüß, S.; Drechsler, R.

https://doi.org/10.1109/TEST.2010.5699289

2010 // Conference paper

SAT-based ATPG for reversible circuits

IDT'10 - 2010 5th International Design and Test Workshop, Proceedings

Zhang, H.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/IDT.2010.5724428

2010 // Book

SMT-based stimuli generation in the SystemC verification library

Lecture Notes in Electrical Engineering

Wille, R.; Große, D.; Haedicke, F.; Drechsler, R.

https://doi.org/10.1007/978-90-481-9304-2_14

2010 // Book

Synthesis of boolean functions in reversible logic

Synthesis Lectures on Digital Circuits and Systems

Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-76249101811&partnerID=MN8TOARS

2010 // Conference paper

Synthesizing multiplier in reversible logic

Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Offermann, S.; Wille, R.; Dueck, G.W.; Drechsler, R.

https://doi.org/10.1109/DDECS.2010.5491757

2010 // Journal article

Synthesizing Reversible Logic,Synthese reversibler Logik

IT - Information Technology

Wille, R.; Drechsler, R.

https://doi.org/10.1524/itit.2010.0568

2010 // Conference paper

SyReC: A programming language for synthesis of reversible circuits

IET Seminar Digest

Wille, R.; Offermann, S.; Drechsler, R.

https://doi.org/10.1049/ic.2010.0150

2010 // Book

Towards a design flow for reversible logic

Towards a Design Flow for Reversible Logic

Wille, R.; Drechsler, R.

https://doi.org/10.1007/978-90-481-9579-4

2010 // Conference paper

Towards analyzing functional coverage in SystemC TLM property checking

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Le, H.M.; Große, D.; Drechsler, R.

https://doi.org/10.1109/HLDVT.2010.5496658

2010 // Journal article

Towards fully automatic synthesis of embedded software

IEEE Embedded Systems Letters

Kühne, U.; Große, D.; Drechsler, R.

https://doi.org/10.1109/LES.2010.2049983

2010 // Conference paper

Towards unifying localization and explanation for automated debugging

Proceedings - International Workshop on Microprocessor Test and Verification

Fey, G.; Sülflow, A.; Drechsler, R.

https://doi.org/10.1109/MTV.2010.10

2010 // Conference paper

Using QBF to increase accuracy of SAT-based debugging

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Sülflow, A.; Fey, G.; Drechsler, R.

https://doi.org/10.1109/ISCAS.2010.5537506

2010 // Conference paper

Verifying UML/OCL models using boolean satisfiability

Proceedings -Design, Automation and Test in Europe, DATE

Soeken, M.; Wille, R.; Kuhlmann, M.; Gogolla, M.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-77953100008&partnerID=MN8TOARS

2010 // Conference paper

Window optimization of reversible and quantum circuits

Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Soeken, M.; Wille, R.; Dueck, G.W.; Drechsler, R.

https://doi.org/10.1109/DDECS.2010.5491754

2009 // Conference paper

A fast untestability proof for SAT-based ATPG

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009

Tille, D.; Drechsler, R.

https://doi.org/10.1109/DDECS.2009.5012096

2009 // Journal article

Advanced verification by automatic property generation

IET Computers and Digital Techniques

Rogin, F.; Klotz, T.; Fey, G.; Drechsler, R.; Rülke, S.

https://doi.org/10.1049/iet-cdt.2008.0110

2009 // Conference paper

Approximate BDD minimization by weighted A

Proceedings - IEEE International Symposium on Circuits and Systems

Ebendt, R.; Drechsler, R.

https://doi.org/10.1109/ISCAS.2009.5118427

2009 // Conference paper

Automatic debugging of system-on-a-chip designs

Proceedings - IEEE International SOC Conference, SOCC 2009

Rogin, F.; Drechsler, R.; Rülke, S.

https://doi.org/10.1109/SOCCON.2009.5398027

2009 // Conference paper

BDD-based synthesis of reversible logic for large functions

Proceedings - Design Automation Conference

Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-70350712413&partnerID=MN8TOARS

2009 // Conference paper

Computing bounds for fault tolerance using formal techniques

Proceedings - Design Automation Conference

Fey, G.; Sülflow, A.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-70350743260&partnerID=MN8TOARS

2009 // Conference paper

Contradictory antecedent debugging in bounded model checking

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Große, D.; Wille, R.; Kühne, U.; Drechsler, R.

https://doi.org/10.1145/1531542.1531587

2009 // Book

Debugging contradictory constraints in constraint-based random simulation

Lecture Notes in Electrical Engineering

Große, D.; Wille, R.; Siegmund, R.; Drechsler, R.

https://doi.org/10.1007/978-1-4020-9714-0_18

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Prof. Rolf Drechsler

Ökosystem

Publikationen

Reducing the number of lines in reversible circuits

RobuCheck: A robustness checker for digital circuits

RobuCheck: A robustness checker for digital circuits

Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability

SAT-based ATPG for reversible circuits

SMT-based stimuli generation in the SystemC verification library

Synthesis of boolean functions in reversible logic

Synthesizing multiplier in reversible logic

Synthesizing Reversible Logic,Synthese reversibler Logik

SyReC: A programming language for synthesis of reversible circuits

Towards a design flow for reversible logic

Towards analyzing functional coverage in SystemC TLM property checking

Towards fully automatic synthesis of embedded software

Towards unifying localization and explanation for automated debugging

Using QBF to increase accuracy of SAT-based debugging

Verifying UML/OCL models using boolean satisfiability

Window optimization of reversible and quantum circuits

A fast untestability proof for SAT-based ATPG

Advanced verification by automatic property generation

Approximate BDD minimization by weighted A

Automatic debugging of system-on-a-chip designs

BDD-based synthesis of reversible logic for large functions

Computing bounds for fault tolerance using formal techniques

Contradictory antecedent debugging in bounded model checking

Debugging contradictory constraints in constraint-based random simulation

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