Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

2009 // Conference paper

Debugging Toffoli Networks

Proceedings -Design, Automation and Test in Europe, DATE

Wille, R.; Große, D.; Frehse, S.; Dueck, G.W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-70350059427&partnerID=MN8TOARS

2009 // Journal article

Efficient Satisfiability Solving Algorithms for Test Pattern Generation, Efficient Satisfiability Algorithms for Test Pattern Generation

IT - Information Technology

Drechsler, R.; Eggersglüß, S.; Fey, G.; Schlöffel, J.; Tille, D.

https://doi.org/10.1524/itit.2009.0529

2009 // Conference paper

Equivalence checking of reversible circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Wille, R.; Grobe, D.; Miller, M.D.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2009.19

2009 // Conference paper

Evaluation of Cardinality Constraints in SMT-Based Debugging

Proceedings of The International Symposium on Multiple-Valued Logic

Sülflow, A.; Wille, R.; Fey, G.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2009.28

2009 // Journal article

Exact synthesis of Toffoli networks with multiple controls using SAT techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Große, D.; Wille, R.; Dueck, G.W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-77955188604&partnerID=MN8TOARS

2009 // Journal article

Exact synthesis of Toffoli networks with multiple controls using SAT techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Große, D.; Wille, R.; Dueck, G.W.; Drechsler, R.

https://doi.org/10.1109/TCAD.2009.2017215

2009 // Journal article

Exact Synthesis of Elementary Quantum Gate Circuits

Journal of Multiple-Valued Logic and Soft Computing

Grobe, D.; Wille, R.; Dueck, G.W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-70449394629&partnerID=MN8TOARS

2009 // Conference paper

Increasing the Robustness of SAT-Based Delay Test Generation Using Efficient Dynamic Learning Techniques

Proceedings of the 14th IEEE European Test Symposium, ETS 2009

Eggersglüß, S.; Drechsler, R.

https://doi.org/10.1109/ETS.2009.13

2009 // Conference paper

Improving the Accuracy of SAT-Based Debugging

Proceedings -Design, Automation and Test in Europe, DATE

Sülflow, A.; Fey, G.; Braunstein, C.; Kühne, U.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-70350072658&partnerID=MN8TOARS

2009 // Conference paper

Induction-Based Formal Verification of SystemC TLM Designs

Proceedings - International Workshop on Microprocessor Test and Verification

Große, D.; Le, H.M.; Drechsler, R.

https://doi.org/10.1109/MTV.2009.16

2009 // Book

Non-clausal SAT and ATPG

Frontiers in Artificial Intelligence and Applications

Drechsler, R.; Junttila, T.; Niemelä, I.

https://doi.org/10.3233/978-1-58603-929-5-655

2009 // Conference paper

Overcoming the Limitations of SystemC Data Introspection

Proceedings -Design, Automation and Test in Europe, DATE

Genz, C.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-70350074641&partnerID=MN8TOARS

2009 // Conference paper

Understanding Property Analysis and Design

Proceedings -Design, Automation and Test in Europe, DATE

Kühne, U.; Große, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-70350055181&partnerID=MN8TOARS

2009 // Conference paper

Reversible Logic Synthesis with Output Permutation

Proceedings: 22nd International Conference on VLSI Design—Held Jointly with the 7th International Conference on Embedded Systems

Wille, R.; Große, D.; Dueck, G.W.; Drechsler, R.

https://doi.org/10.1109/VLSI.Design.2009.40

2009 // Conference paper

Robustness Check for Multiple Faults Using Formal Techniques

12th Euromicro Conference on Digital System Design: Architectures, Methods, and Tools, DSD 2009

Frehse, S.; Fey, G.; Sülflow, A.; Drechsler, R.

https://doi.org/10.1109/DSD.2009.218

2009 // Conference paper

SMT-Based Stimuli Generation in the SystemC Verification Library

2009 Forum on Specification and Design Languages, FDL 2009

Wille, R.; Große, D.; Haedicke, F.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-77951588560&partnerID=MN8TOARS

2009 // Conference paper

Speeding Up SAT-Based ATPG Using Dynamic Clause Activation

Proceedings of the Asian Test Symposium

Eggersglüß, S.; Tille, D.; Drechsler, R.

https://doi.org/10.1109/ATS.2009.26

2009 // Conference paper

Structural Heuristics for SAT-Based ATPG

Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009

Tille, D.; Eggersglüß, S.; Le, H.M.; Drechsler, R.

https://doi.org/10.1109/VLSISOC.2009.6041334

2009 // Book

SWORD: A SAT-like prover that uses word-level information

IFIP International Federation for Information Processing

Wille, R.; Fey, G.; Große, D.; Eggersglüß, S.; Drechsler, R.

https://doi.org/10.1007/978-0-387-89558-1_10

2009 // Book

Test pattern generation using Boolean proof engines

Test Pattern Generation Using Boolean Proof Engines

Drechsler, R.; Eggersglüß, S.; Fey, G.; Tille, D.

https://doi.org/10.1007/978-90-481-2360-5

2009 // Conference paper

Timing-arc-based logic analysis for false noise reduction

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Palla, M.; Bargfrede, J.; Eggersglüß, S.; Anheier, W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-76349112249&partnerID=MN8TOARS

2009 // Conference paper

Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation

2009 10th Latin American Test Workshop, LATW 2009

Messing, M.; Glowatz, A.; Hapke, F.; Drechsler, R.

https://doi.org/10.1109/LATW.2009.4813791

2009 // Journal article

Weighted A<sup>*</sup> search - unifying view and application

Artificial Intelligence

Ebendt, R.; Drechsler, R.

https://doi.org/10.1016/j.artint.2009.06.004

2009 // Conference paper

WoLFram - A word-level framework for formal verification

Proceedings of the International Workshop on Rapid System Prototyping

Sülflow, A.; Kühne, U.; Fey, G.; Große, D.; Drechsler, R.

https://doi.org/10.1109/RSP.2009.21

2008 // Conference paper

A Basis for Formal Robustness Checking

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Fey, G.; Drechsler, R.

https://doi.org/10.1109/ISQED.2008.4479838

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Prof. Rolf Drechsler

Ecosystem

Publications

Debugging Toffoli Networks

Efficient Satisfiability Solving Algorithms for Test Pattern Generation, Efficient Satisfiability Algorithms for Test Pattern Generation

Equivalence checking of reversible circuits

Evaluation of Cardinality Constraints in SMT-Based Debugging

Exact synthesis of Toffoli networks with multiple controls using SAT techniques

Exact synthesis of Toffoli networks with multiple controls using SAT techniques

Exact Synthesis of Elementary Quantum Gate Circuits

Increasing the Robustness of SAT-Based Delay Test Generation Using Efficient Dynamic Learning Techniques

Improving the Accuracy of SAT-Based Debugging

Induction-Based Formal Verification of SystemC TLM Designs

Non-clausal SAT and ATPG

Overcoming the Limitations of SystemC Data Introspection

Understanding Property Analysis and Design

Reversible Logic Synthesis with Output Permutation

Robustness Check for Multiple Faults Using Formal Techniques

SMT-Based Stimuli Generation in the SystemC Verification Library

Speeding Up SAT-Based ATPG Using Dynamic Clause Activation

Structural Heuristics for SAT-Based ATPG

SWORD: A SAT-like prover that uses word-level information

Test pattern generation using Boolean proof engines

Timing-arc-based logic analysis for false noise reduction

Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation

Weighted A<sup>*</sup> search - unifying view and application

WoLFram - A word-level framework for formal verification

A Basis for Formal Robustness Checking

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions