Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

2008 // Conference paper

Adaptive branch-and-bound using SAT to estimate false crosstalk

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Palla, M.; Bargfrede, J.; Koch, K.; Anheier, W.; Drechsler, R.

https://doi.org/10.1109/ISQED.2008.4479787

2008 // Book

An integrated SystemC debugging environment

Lecture Notes in Electrical Engineering

Rogin, F.; Genz, C.; Drechsler, R.; Rülke, S.

https://doi.org/10.1007/978-1-4020-8297-9_5

2008 // Journal article

Analyzing Functional Coverage in Bounded Model Checking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Große, D.; Kühne, U.; Drechsler, R.

https://doi.org/10.1109/TCAD.2008.925790

2008 // Journal article

Automatic Fault Localization for Property Checking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Fey, G.; Staber, S.; Bloem, R.; Drechsler, R.

https://doi.org/10.1109/TCAD.2008.923234

2008 // Conference paper

Automatic generation of complex properties for hardware designs

Proceedings -Design, Automation and Test in Europe, DATE

Rogin, F.; Klotz, T.; Fey, G.; Drechsler, R.; Rülke, S.

https://doi.org/10.1109/DATE.2008.4484908

2008 // Conference paper

A Comparative Study Based on Solving the Test Compaction Problem

Proceedings of The International Symposium on Multiple-Valued Logic

Logofǎtu, D.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2008.17

2008 // Conference paper

Contradiction Analysis for Constraint-Based Random Simulation

Proceedings - 2008 Forum on Specification, Verification, and Design Languages, FDL'08

Große, D.; Wille, R.; Siegmund, R.; Drechsler, R.

https://doi.org/10.1109/FDL.2008.4641434

2008 // Conference paper

Exact synthesis of elementary quantum gate circuits for reversible functions with "don't cares"

Proceedings of The International Symposium on Multiple-Valued Logic

Große, D.; Wille, R.; Dueck, G.W.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2008.42

2008 // Conference paper

Identifying a subset of SystemVerilog assertions for efficient bounded model checking

Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods, and Tools, DSD 2008

Wille, R.; Fey, G.; Messing, M.; Angst, G.; Linhard, L.; Drechsler, R.

https://doi.org/10.1109/DSD.2008.53

2008 // Conference paper

Incremental SAT Instance Generation for SAT-Based ATPG

Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Tille, D.; Drechsler, R.

https://doi.org/10.1109/DDECS.2008.4538759

2008 // Book

Lecture Notes in Computer Science (including the subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Giacobini, M.; Di Caro, G.A.; Esparcia-Alcázar, A.I.; McCormack, J.; Rothlauf, F.; Yang, S.; Brabazon, A.; Drechsler, R.; Farooq, M.; O'Neill, M.; Squillero, G.; Cagnoni, S.; Ekárt, A.; Fink, A.; Romero, J.; Uyar, A.S.

http://www.scopus.com/inward/record.url?eid=2-s2.0-47249128141&partnerID=MN8TOARS

2008 // Journal article

Logic Minimization and Testability of 2-SPP Networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Bernasconi, A.; Ciriani, V.; Drechsler, R.; Villa, T.

https://doi.org/10.1109/TCAD.2008.923072

2008 // Book

Measuring the Quality of a SystemC Testbench Using Code Coverage Techniques

Lecture Notes in Electrical Engineering

Große, D.; Peraza, H.; Klingauf, W.; Drechsler, R.

https://doi.org/10.1007/978-1-4020-8297-9_6

2008 // Journal article

Modeling and Proving Functional Completeness in the Formal Verification of Counting Heads

International Journal on Software Tools for Technology Transfer

Kinder, S.; Drechsler, R.

https://doi.org/10.1007/s10009-008-0084-z

2008 // Journal article

On Accelerating SAT-Based ATPG for Industrial Designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Drechsler, R.; Eggersglüß, S.; Fey, G.; Glowatz, A.; Hapke, F.; Schloeffel, J.; Tille, D.

https://doi.org/10.1109/TCAD.2008.923107

2008 // Journal article

On the Design of Small, Fully Testable Circuits with Low Depth

Microprocessors and Microsystems

Fey, G.; Bernasconi, A.; Ciriani, V.; Drechsler, R.

https://doi.org/10.1016/j.micpro.2008.03.005

2008 // Conference paper

On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults

Proceedings of The International Symposium on Multiple-Valued Logic

Eggersglüß, S.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2008.19

2008 // Conference paper

Robust on-chip bus architecture synthesis for MPSoCs that accounts for process variations

Proceedings - IEEE International Symposium on Circuits and Systems

Pandey, S.; Drechsler, R.; Murgan, T.; Glesner, M.

https://doi.org/10.1109/ISCAS.2008.4542086

2008 // Conference paper

Understanding Property Analysis and Design in a Quality-Driven Bounded Model Checking Workflow

Proceedings - International Workshop on Microprocessor Test and Verification

Kühne, U.; Große, D.; Drechsler, R.

https://doi.org/10.1109/MTV.2008.17

2008 // Conference paper

RevLib: An online resource for reversible functions and reversible circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Wille, R.; Große, D.; Teuber, L.; Dueck, G.W.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2008.43

2008 // Conference paper

Robust On-Chip Bus Architecture Synthesis for MPSoCs Under Random Task Arrival

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Pandey, S.; Drechsler, R.

https://doi.org/10.1109/ASPDAC.2008.4484022

2008 // Book

Robustness and Usability in Modern Design Workflows

Fey, G.; Drechsler, R.

https://doi.org/10.1007/978-1-4020-6536-1

2008 // Conference paper

Slack-Allocation-Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

Proceedings -Design, Automation and Test in Europe, DATE

Pandey, S.; Drechsler, R.

https://doi.org/10.1109/DATE.2008.4484687

2008 // Conference paper

Using Higher Levels of Abstraction to Solve Optimization Problems via Boolean Satisfiability

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Wille, R.; Große, D.; Soeken, M.; Drechsler, R.

https://doi.org/10.1109/ISVLSI.2008.82

2008 // Conference paper

Using unsatisfiable cores to debug multiple design errors

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Sülflow, A.; Fey, G.; Bloem, R.; Drechsler, R.

https://doi.org/10.1145/1366110.1366131

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Prof. Rolf Drechsler

Ecosystem

Publications

Adaptive branch-and-bound using SAT to estimate false crosstalk

An integrated SystemC debugging environment

Analyzing Functional Coverage in Bounded Model Checking

Automatic Fault Localization for Property Checking

Automatic generation of complex properties for hardware designs

A Comparative Study Based on Solving the Test Compaction Problem

Contradiction Analysis for Constraint-Based Random Simulation

Exact synthesis of elementary quantum gate circuits for reversible functions with "don't cares"

Identifying a subset of SystemVerilog assertions for efficient bounded model checking

Incremental SAT Instance Generation for SAT-Based ATPG

Lecture Notes in Computer Science (including the subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface

Logic Minimization and Testability of 2-SPP Networks

Measuring the Quality of a SystemC Testbench Using Code Coverage Techniques

Modeling and Proving Functional Completeness in the Formal Verification of Counting Heads

On Accelerating SAT-Based ATPG for Industrial Designs

On the Design of Small, Fully Testable Circuits with Low Depth

On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults

Robust on-chip bus architecture synthesis for MPSoCs that accounts for process variations

Understanding Property Analysis and Design in a Quality-Driven Bounded Model Checking Workflow

RevLib: An online resource for reversible functions and reversible circuits

Robust On-Chip Bus Architecture Synthesis for MPSoCs Under Random Task Arrival

Robustness and Usability in Modern Design Workflows

Slack-Allocation-Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs

Using Higher Levels of Abstraction to Solve Optimization Problems via Boolean Satisfiability

Using unsatisfiable cores to debug multiple design errors

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions