2022 // conference-paper
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
Proceedings - 2022 25th Euromicro Conference on Digital System Design, DSD 2022
Kole, A.; Datta, K.; Sengupta, I.; Drechsler, R.
DOI: 10.1109/DSD57027.2022.00108
2022 // conference-paper
Polynomial Formal Verification of General Tree-Like Circuits
2022 China Semiconductor Technology International Conference, CSTIC 2022
Mahzoon, A.; Drechsler, R.
DOI: 10.1109/CSTIC55103.2022.9856884
2022 // conference-paper
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Proceedings of the European Test Workshop
Merten, M.; Huhn, S.; Drechsler, R.
DOI: 10.1109/ETS54262.2022.9810459
2022 // conference-paper
Polynomial formal verification: ensuring correctness under resource constraints
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Drechsler, R.; Mahzoon, A.
DOI: 10.1145/3508352.3561104
2022 // conference-paper
Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic
Proceedings of The International Symposium on Multiple-Valued Logic
Niemann, P.; Drechsler, R.
DOI: 10.1109/ISMVL52857.2022.00009
2022 // journal-article
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware
Journal of Systems Architecture
Tempel, S.; Herdt, V.; Drechsler, R.
DOI: 10.1016/j.sysarc.2022.102456
2022 // conference-paper
Polynomial Formal Verification of Complex Multipliers
MBMV 2022: Methods and Description Languages for Modeling and Verification of Circuits and Systems - 25th Workshop
Mahzoon, A.; Drechsler, R.
DOI:
2022 // conference-paper
RISC-V Processor Verification with Coverage-guided Aging
MBMV 2022: Methods and Description Languages for Modeling and Verification of Circuits and Systems - 25th Workshop
Bruns, N.; Herdt, V.; Jentzsch, E.; Drechsler, R.
DOI:
2022 // other
Simulation-based Verification of SystemC-based VPs at the ESL
arXiv
Goli, M.; Drechsler, R.
DOI:
2022 // conference-paper
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection
Proceedings of the IEEE VLSI Test Symposium
Merten, M.; Huhn, S.; Drechsler, R.
DOI: 10.1109/VTS52500.2021.9794161
2022 // conference-paper
Preserving Design Hierarchy Information for Polynomial Formal Verification
IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Drechsler, R.; Mahzoon, A.
DOI: 10.1109/VLSI-SoC54400.2022.9939650
2022 // conference-paper
Adapting mutation and recombination operators to range-aware relations in real-world application data
GECCO 2022 Companion - Proceedings of the 2022 Genetic and Evolutionary Computation Conference
Plump, C.; Berger, B.J.; Drechsler, R.
DOI: 10.1145/3520304.3529066
2022 // conference-paper
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Proceedings - International Test Conference
Huhn, S.; Drechsler, R.
DOI: 10.1109/ITC50671.2022.00086
2022 // conference-paper
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability
Proceedings - Design Automation Conference
Mahzoon, A.; Große, D.; Scholl, C.; Konrad, A.; Drechsler, R.
DOI: 10.1145/3489517.3530605
2022 // conference-paper
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling
MLCAD 2022 - Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD
Metz, C.A.; Goli, M.; Drechsler, R.
DOI: 10.1145/3551901.3556481
2022 // conference-paper
Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-based Memristor Design Style
2022 IEEE International Conference on Emerging Electronics, ICEE 2022
Jha, C.K.; Mahzoon, A.; Drechsler, R.
DOI: 10.1109/ICEE56203.2022.10117915
2022 // conference-paper
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs
Proceedings - 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022
Metz, C.A.; Goli, M.; Drechsler, R.
DOI: 10.1109/DDECS54261.2022.9770153
2022 // conference-paper
Towards Polynomial Formal Verification of Complex Arithmetic Circuits
Proceedings - 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022
Drechsler, R.; Mahzoon, A.; Goli, M.
DOI: 10.1109/DDECS54261.2022.9770156
2022 // conference-paper
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools
Proceedings - Design Automation Conference
Pieper, P.; Herdt, V.; Große, D.; Drechsler, R.
DOI: 10.1145/3489517.3530604
2022 // conference-paper
Design Modification for Polynomial Formal Verification
Proceedings - 2022 International Symposium on Electrical, Electronics and Information Engineering, ISEEIE 2022
Drechsler, R.; Mahzoon, A.
DOI: 10.1109/ISEEIE55684.2022.00040
2022 // conference-paper
ANN-based Performance Estimation of Embedded Software for RISC-V Processors
Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP
Zhang, W.; Goli, M.; Mahzoon, A.; Drechsler, R.
DOI: 10.1109/RSP57251.2022.10039004
2022 // conference-paper
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture
Proceedings of The International Symposium on Multiple-Valued Logic
Datta, K.; Kole, A.; Sengupta, I.; Drechsler, R.
DOI: 10.1109/ISMVL52857.2022.00013
2022 // conference-paper
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Proceedings - 2022 25th Euromicro Conference on Digital System Design, DSD 2022
Ahmadi-Pour, S.; Saha, S.; Herdt, V.; Drechsler, R.; McDonald-Maier, K.
DOI: 10.1109/DSD57027.2022.00027
2022 // journal-article
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research
Journal of Systems Architecture
Ahmadi-Pour, S.; Herdt, V.; Drechsler, R.
DOI: 10.1016/j.sysarc.2022.102757
2022 // conference-paper
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Parvin, S.; Krachenfels, T.; Tajik, S.; Seifert, J.-P.; Torres, F.S.; Drechsler, R.
DOI: 10.1109/ASP-DAC52403.2022.9712518
