Prof. Rolf Drechsler

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Mitglied des Direktoriums des Wissenschaftsschwerpunkts "Minds, Media, Machines"

Leiter der Arbeitsgruppe Rechnerarchitektur

Direktor der Gruppe Cyber Physical Systems am Deutschen Forschungszentrum für Künstliche Intelligenz (DFKI)

Mitgründer und Sprecher des Data Science Center (DSC) an der Universität Bremen

Dekan des Fachbereichs 3 Mathematik/Informatik

Betreuer für das Graduiertenkolleg „CAUSE“

Mitglied des CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Mitglied des Direktoriums des Forschungscluster "Logdynamics"

Publikationen

2015 // Journal article

Scalable one-pass synthesis for digital microfluidic biochips

IEEE Design and Test

Wille, R.; Keszocze, O.; Drechsler, R.; Boehnisch, T.; Kroker, A.

https://doi.org/10.1109/MDAT.2015.2455344

2015 // Book

Technology mapping for single target gate based circuits using boolean functional decomposition

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Abdessaied, N.; Soeken, M.; Drechsler, R.

https://doi.org/10.1007/978-3-319-20860-2_14

2015 // Conference paper

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

CEUR Workshop Proceedings

Przigoda, N.; Peters, J.; Soeken, M.; Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84960964764&partnerID=MN8TOARS

2015 // Conference paper

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

CEUR Workshop Proceedings

Przigoda, N.; Peters, J.; Soeken, M.; Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84960964764&partnerID=MN8TOARS

2015 // Conference paper

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

CEUR Workshop Proceedings

Przigoda, N.; Peters, J.; Soeken, M.; Wille, R.; Drechsler, R.

2015 // Conference paper

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

CEUR Workshop Proceedings

Przigoda, N.; Peters, J.; Soeken, M.; Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84960964764&partnerID=MN8TOARS

2015 // Book

Towards line-aware realizations of expressions for HDL-based synthesis of reversible circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Al-Wardi, Z.; Wille, R.; Drechsler, R.

https://doi.org/10.1007/978-3-319-20860-2_15

2015 // Conference paper

Verification-driven design across abstraction levels: A case study

Proceedings - 18th Euromicro Conference on Digital System Design, DSD 2015

Przigoda, N.; Stoppe, J.; Seiter, J.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/DSD.2015.88

2015 // Conference paper

Verifying consistency between activity diagrams and their corresponding OCL contracts

Forum on Specification and Design Languages

Hilken, C.; Seiter, J.; Wille, R.; Kuhne, U.; Drechsler, R.

https://doi.org/10.1109/FDL.2014.7119340

2015 // Conference paper

Verifying SystemC using stateful symbolic simulation

Proceedings - Design Automation Conference

Herdt, V.; Le, H.M.; Drechsler, R.

https://doi.org/10.1145/2744769.2744927

2014 // Conference paper

A cube pairing approach for synthesis of ESOP-based reversible circuit

Proceedings of The International Symposium on Multiple-Valued Logic

Bandyopadhyay, C.; Rahaman, H.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2014.27

2014 // Book

An approach to reversible logic synthesis using input and output permutations

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Datta, K.; Sengupta, I.; Rahaman, H.; Drechsler, R.

https://doi.org/10.1007/978-3-662-45711-56

2014 // Journal article

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques

IT - Information Technology

Eggersglü, S.; Drechsler, R.

https://doi.org/10.1515/itit-2013-1041

2014 // Book

Behaviour driven development for tests and verification

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Diepenbeck, M.; Kühne, U.; Soeken, M.; Drechsler, R.

https://doi.org/10.1007/978-3-319-09099-3_5

2014 // Journal article

Considering nearest neighbor constraints of quantum circuits at the reversible circuit level

Quantum Information Processing

Wille, R.; Lye, A.; Drechsler, R.

https://doi.org/10.1007/s11128-013-0642-5

2014 // Conference paper

Determining cases of scenarios to improve coverage in simulation-based verification

Proceedings, SBCCI 2014 - 27th Symposium on Integrated Circuits and Systems Design: Chip in Aracaju

Yang, S.; Wille, R.; Drechsler, R.

https://doi.org/10.1145/2660540.2660979

2014 // Conference paper

Efficient synthesis of quantum circuits implementing clifford group operations

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Niemann, P.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/ASPDAC.2014.6742938

2014 // Book

Equivalence checking in multi-level quantum systems

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Niemann, P.; Wille, R.; Drechsler, R.

https://doi.org/10.1007/978-3-319-08494-7_16

2014 // Conference paper

Exact one-pass synthesis of digital microfluidic biochips

Proceedings - Design Automation Conference

Keszocze, O.; Wille, R.; Ho, T.-Y.; Drechsler, R.

https://doi.org/10.1145/2593069.2593135

2014 // Journal article

Exact reordering of circuit lines for nearest neighbor quantum architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Wille, R.; Lye, A.; Drechsler, R.

https://doi.org/10.1109/TCAD.2014.2356463

2014 // Book

Formal specification level

Lecture Notes in Electrical Engineering

Drechsler, R.; Soeken, M.; Wille, R.

https://doi.org/10.1007/978-3-319-01418-0_3

2014 // Conference paper

Generating SystemC implementations for clock constraints specified in UML/MARTE CCSL

Proceedings of the IEEE International Conference on Engineering of Complex Computer Systems, ICECCS

Peters, J.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/ICECCS.2014.24

2014 // Book

Improved cube list based cube pairing approach for synthesis of ESOP based reversible logic

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Bandyopadhyay, C.; Rahaman, H.; Drechsler, R.

https://doi.org/10.1007/978-3-662-45711-5_8

2014 // Conference paper

Improving coverage of simulation-based verification by dedicated stimuli generation

Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014

Yang, S.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/DSD.2014.100

2014 // Journal article

Introduction to the special issue on reversible computation

ACM Journal on Emerging Technologies in Computing Systems

Wille, R.; Drechsler, R.; Tahoori, M.B.

https://doi.org/10.1145/2663349

«‹20 / 39›»

Prof. Rolf Drechsler

Ökosystem

Publikationen

Scalable one-pass synthesis for digital microfluidic biochips

Technology mapping for single target gate based circuits using boolean functional decomposition

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

Towards an automatic approach for restricting UML/OCL invariability clauses (Work-in-Progress Report)

Towards line-aware realizations of expressions for HDL-based synthesis of reversible circuits

Verification-driven design across abstraction levels: A case study

Verifying consistency between activity diagrams and their corresponding OCL contracts

Verifying SystemC using stateful symbolic simulation

A cube pairing approach for synthesis of ESOP-based reversible circuit

An approach to reversible logic synthesis using input and output permutations

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques

Behaviour driven development for tests and verification

Considering nearest neighbor constraints of quantum circuits at the reversible circuit level

Determining cases of scenarios to improve coverage in simulation-based verification

Efficient synthesis of quantum circuits implementing clifford group operations

Equivalence checking in multi-level quantum systems

Exact one-pass synthesis of digital microfluidic biochips

Exact reordering of circuit lines for nearest neighbor quantum architectures

Formal specification level

Generating SystemC implementations for clock constraints specified in UML/MARTE CCSL

Improved cube list based cube pairing approach for synthesis of ESOP based reversible logic

Improving coverage of simulation-based verification by dedicated stimuli generation

Introduction to the special issue on reversible computation

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.