Symbolic simulation using decision diagrams

Electronics Letters

Sympathy-MV: fast exact minimization of fixed polarity multi-valued linear expressions

Proceedings of The International Symposium on Multiple-Valued Logic

Sympathy: Fast exact minimization of fixed polarity reed-muller expressions for symmetric functions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Ternary and Quaternary Lattice Diagrams for Linearly-Independent Logic, multiple-valued logic, and analog synthesis

Proceedings of the International Conference on Information, Communications and Signal Processing, ICICS

Testability of 2-Level AND/EXOR circuits

Proceedings of the 1997 European Conference on Design and Test, EDTC 1997

Testability of 2-level AND/EXOR circuits

Proceedings of European Design and Test Conference

The K*BMD: A verification data structure

IEEE Design and Test of Computers

A fast optimal robust path delay fault testable adder

Proceedings of the 1996 European Conference on Design and Test, EDTC 1996

AND/EXOR-based synthesis of testable KFDD-circuits with small depth

Proceedings of the Asian Test Symposium

Exact minimisation of Kronecker expressions for symmetric functions

IEE Proceedings: Computers and Digital Techniques

Exact minimization of Kronecker expressions for symmetric functions

Proceedings - IEEE International Symposium on Circuits and Systems

Fast OFDD-based minimization of fixed polarity Reed-Muller expressions

IEEE Transactions on Computers

Fast optimal robust path delay fault testable adder

Proceedings of European Design and Test Conference

Genetic algorithm for variable ordering of OBDDs

IEE Proceedings: Computers and Digital Techniques

Hybrid genetic algorithm for the channel routing problem

Proceedings - IEEE International Symposium on Circuits and Systems

K*BMDs: A new data structure for verification

Proceedings of European Design and Test Conference

K∗BMDs: A new data structure for verification

Proceedings of the 1996 European Conference on Design and Test, EDTC 1996

Learning heuristics for OBDD minimization by evolutionary algorithms

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

MORE: an alternative implementation of BDD packages by multi-operand synthesis

European Design Automation Conference - Proceedings

Relation between OFDDs and FPRMs

Electronics Letters

Verification of multi-valued logic networks

Proceedings of The International Symposium on Multiple-Valued Logic

Dynamic minimization of OKFDDs

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Genetic algorithm for decomposition type choice in OKFDDs

How many decomposition types do we need ?

Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

Learning heuristics by genetic algorithms

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC