Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

ACM Transactions on Embedded Computing Systems

AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

Exploiting the Extended Neighborhood of Hexagonal Qubit Architecture for Mapping Quantum Circuits

ACM Journal on Emerging Technologies in Computing Systems

EvoAl - Codeless Domain-Optimisation

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification

cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing

IEEE Transactions on Circuits and Systems I: Regular Papers

PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor

Polynomial Formal Verification exploiting Constant Cutwidth

Polynomial Formal Verification of KFDD Circuits

Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Chips

Scalable Neuroevolution of Ensemble Learners

Repetitive Processes and Their Surrogate-Model Congruent Encoding for Evolutionary Algorithms - A Theoretic Proposal

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors

IEEE Transactions on Circuits and Systems II: Express Briefs

Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT

IEEE Internet of Things Journal

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture

EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures

Finite State Automata Design using 1T1R ReRAM Crossbar

arXiv

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans-A RISC-V Case Study

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Polynomial Formal Verification of a Processor: A RISC-V Case Study

Proceedings - International Symposium on Quality Electronic Design, ISQED

A Class of Polynomially Verifiable Circuits of Logarithmic Depth

Proceedings of the 13th International Conference on Cloud Computing, Data Science and Engineering, Confluence 2023

Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine

Impact of sneak paths on in-memory logic design in memristive crossbars

IT - Information Technology