Automated polynomial formal verification using generalized binary decision diagram patterns

Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences

Exploration of Design Alternatives for Reducing Idle Time in Shor's Algorithm: A Study on Monolithic and Distributed Quantum Systems

IEEE Transactions on Quantum Engineering

Polynomial Formal Verification of a RISC-V Processor

IEEE Transactions on Nanotechnology

Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth

IEEE Transactions on Circuits and Systems I: Regular Papers

ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars

ACM Transactions on Embedded Computing Systems

Determining the Effect of Feedback Quality on User Engagement on Online Idea Crowdsourcing Platforms Using an AI model

Proceedings of the ACM on Human-Computer Interaction

Exploiting the Extended Neighborhood of Hexagonal Qubit Architecture for Mapping Quantum Circuits

ACM Journal on Emerging Technologies in Computing Systems

Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL

ACM Transactions on Embedded Computing Systems

AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

Why less is sometimes more

it - Information Technology

EvoAl - Codeless Domain-Optimisation

Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent

Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification

cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

Timed-Vp: Early and Configurable Timing Estimation Models for Virtual Prototypes

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing

IEEE Transactions on Circuits and Systems I: Regular Papers

PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor

Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification

Polynomial Formal Verification exploiting Constant Cutwidth

Polynomial Formal Verification of KFDD Circuits

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Chips

Repetitive Processes and Their Surrogate-Model Congruent Encoding for Evolutionary Algorithms - A Theoretic Proposal

Scalable Neuroevolution of Ensemble Learners

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors

IEEE Transactions on Circuits and Systems II: Express Briefs