Wissenschaftsschwerpunkt der

© Jörg Sarbach
© Jörg Sarbach
Prof. Rolf Drechsler

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Publikationen
2023 // journal-article

Improving the Designs of Nearest Neighbour Quantum Circuits for 1D and 2D Architectures

IETE Journal of Research

Bandyopadhyay, C.; Bhattacharjee, A.; Wille, R.; Drechsler, R.; Rahaman, H.
DOI: 10.1080/03772063.2020.1822215

2023 // conference-paper

Polynomial Formal Verification of a Processor: A RISC-V Case Study

Proceedings - International Symposium on Quality Electronic Design, ISQED

Weingarten, L.; Mahzoon, A.; Goli, M.; Drechsler, R.
DOI: 10.1109/ISQED57927.2023.10129397

2023 // journal-article

Impact of sneak paths on in-memory logic design in memristive crossbars

IT - Information Technology

Datta, K.; Deb, A.; Kole, A.; Drechsler, R.
DOI: 10.1515/itit-2023-0020

2023 // other

Finite State Automata Design using 1T1R ReRAM Crossbar

arXiv

Singh, S.; Ghazal, O.; Jha, C.K.; Rana, V.; Drechsler, R.; Shafik, R.; Yakovlev, A.; Patkar, S.; Merchant, F.
DOI: 10.48550/arXiv.2304.13552

2023 // book

Formal verification of structurally complex multipliers

Formal Verification of Structurally Complex Multipliers

Mahzoon, A.; Große, D.; Drechsler, R.
DOI: 10.1007/978-3-031-24571-8

2023 // conference-paper

EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Krauss, R.; Goli, M.; Drechsler, R.
DOI: 10.1145/3566097.3567913

2023 // conference-paper

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans-A RISC-V Case Study

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Parvin, S.; Goli, M.; Torres, F.S.; Drechsler, R.
DOI: 10.1145/3566097.3567919

2023 // other

Lower Bound Proof for the Size of Bdds Representing a Shifted Addition

SSRN

Kleinekathöfer, J.; Mahzoon, A.; Drechsler, R.
DOI:

2023 // conference-paper

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Deb, A.; Datta, K.; Hassan, M.; Shirinzadeh, S.; Drechsler, R.
DOI: 10.1145/3566097.3567842

2023 // conference-paper

A Class of Polynomially Verifiable Circuits of Logarithmic Depth

Proceedings of the 13th International Conference on Cloud Computing, Data Science and Engineering, Confluence 2023

Dominik, C.; Drechsler, R.
DOI: 10.1109/Confluence56041.2023.10048892

Dec 2022 // journal-article

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing

IEEE Embedded Systems Letters

Soren Tempel; Vladimir Herdt; Rolf Drechsler

Dec 2022 // journal-article

IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Chandan Kumar Jha; Phrangboklang Lyngton Thangkhiew; Kamalika Datta; Rolf Drechsler

Sep 2022 // journal-article

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

Journal of Low Power Electronics and Applications

Pascal Pieper; Vladimir Herdt; Rolf Drechsler

Jul 2022 // journal-article

Power-aware test scheduling framework for IEEE 1687 multi-power domain networks using formal techniques

Microelectronics Reliability

Payam Habiby; Sebastian Huhn; Rolf Drechsler

May 2022 // journal-article

RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Alireza Mahzoon; Daniel GroBe; Rolf Drechsler

Apr 2022 // journal-article

Parallel Computing of Graph-based Functions in ReRAM

ACM Journal on Emerging Technologies in Computing Systems

Saman Froehlich; Saeideh Shirinzadeh; Rolf Drechsler

Apr 2022 // journal-article

Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Mehran Goli; Rolf Drechsler

2022 // conference-paper

Mapping Quantum Circuits to 2-Dimensional Quantum Architectures

Lecture Notes in Informatics (LNI), Proceedings - Series of the Gesellschaft fur Informatik (GI)

Datta, K.; Kole, A.; Sengupta, I.; Drechsler, R.
DOI: 10.18420/inf2022_94

2022 // conference-paper

Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions

Proceedings - 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022

Funck, M.; Herdt, V.; Drechsler, R.
DOI: 10.1109/DDECS54261.2022.9770108

2022 // journal-article

CoMIC: Complementary Memristor based in-memory computing in 3D architecture

Journal of Systems Architecture

Lalchhandama, F.; Datta, K.; Chakraborty, S.; Drechsler, R.; Sengupta, I.
DOI: 10.1016/j.sysarc.2022.102480

2022 // other

Lower Bound Proof for the Size of BDDs representing a Shifted Addition

arXiv

Kleinekathöfer, J.; Mahzoon, A.; Drechsler, R.
DOI: 10.48550/arXiv.2209.12477

2022 // conference-paper

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

Bruns, N.; Herdt, V.; Jentzsch, E.; Drechsler, R.
DOI: 10.23919/DATE54114.2022.9774771

2022 // conference-paper

Monitoring the Effects of Static Variable Orders on the Construction of BDDs

MESIICON 2022 - International Interdisciplinary Conference on Mathematics, Engineering and Science, Proceedings

Qayyum, K.; Mahzoon, A.; Drechsler, R.
DOI: 10.1109/MESIICON55227.2022.10093493

2022 // conference-paper

Polynomial Formal Verification of Approximate Adders

Proceedings - 2022 25th Euromicro Conference on Digital System Design, DSD 2022

Schnieber, M.; Froehlich, S.; Drechsler, R.
DOI: 10.1109/DSD57027.2022.00107

2022 // journal-article

Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits

IT - Information Technology

Froehlich, S.; Drechsler, R.
DOI: 10.1515/itit-2021-0042