Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT

IEEE Internet of Things Journal

A Class of Polynomially Verifiable Circuits of Logarithmic Depth

Proceedings of the 13th International Conference on Cloud Computing, Data Science and Engineering, Confluence 2023

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures

Finite State Automata Design using 1T1R ReRAM Crossbar

arXiv

Formal verification of structurally complex multipliers

Formal Verification of Structurally Complex Multipliers

Impact of sneak paths on in-memory logic design in memristive crossbars

IT - Information Technology

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture

Improving the Designs of Nearest Neighbour Quantum Circuits for 1D and 2D Architectures

IETE Journal of Research

Lower Bound Proof for the Size of Bdds Representing a Shifted Addition

SSRN

Polynomial Formal Verification of a Processor: A RISC-V Case Study

Proceedings - International Symposium on Quality Electronic Design, ISQED

Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans-A RISC-V Case Study

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking

Proceedings - International Symposium on Quality Electronic Design, ISQED

IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits

Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing

IEEE Embedded Systems Letters

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

Journal of Low Power Electronics and Applications

Power-aware test scheduling framework for IEEE 1687 multi-power domain networks using formal techniques

Microelectronics Reliability

RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Parallel Computing of Graph-based Functions in ReRAM

ACM Journal on Emerging Technologies in Computing Systems

Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

3D Visualization of Symbolic Execution Traces

Forum on Specification and Design Languages

A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection

Proceedings of the IEEE VLSI Test Symposium

Adapting mutation and recombination operators to range-aware relations in real-world application data

GECCO 2022 Companion - Proceedings of the 2022 Genetic and Evolutionary Computation Conference