Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification

veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing

IEEE Transactions on Circuits and Systems I: Regular Papers

cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits

IEEE Transactions on Circuits and Systems I: Regular Papers

PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor

Polynomial Formal Verification of KFDD Circuits

Polynomial Formal Verification exploiting Constant Cutwidth

Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Chips

Repetitive Processes and Their Surrogate-Model Congruent Encoding for Evolutionary Algorithms - A Theoretic Proposal

Scalable Neuroevolution of Ensemble Learners

MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors

IEEE Transactions on Circuits and Systems II: Express Briefs

Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT

IEEE Internet of Things Journal

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans-A RISC-V Case Study

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking

Proceedings - International Symposium on Quality Electronic Design, ISQED

Improving the Designs of Nearest Neighbour Quantum Circuits for 1D and 2D Architectures

IETE Journal of Research

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture

A Class of Polynomially Verifiable Circuits of Logarithmic Depth

Proceedings of the 13th International Conference on Cloud Computing, Data Science and Engineering, Confluence 2023

Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Impact of sneak paths on in-memory logic design in memristive crossbars

IT - Information Technology

Polynomial Formal Verification of a Processor: A RISC-V Case Study

Proceedings - International Symposium on Quality Electronic Design, ISQED

Finite State Automata Design using 1T1R ReRAM Crossbar

arXiv

Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine

Lower Bound Proof for the Size of Bdds Representing a Shifted Addition

SSRN

Formal verification of structurally complex multipliers

Formal Verification of Structurally Complex Multipliers