Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

2016 // Journal article

On Optimization-Based ATPG and Its Application to Highly Compacted Test Sets

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Eggersglüß, S.; Schmitz, K.; Krenz-Bååth, R.; Drechsler, R.

https://doi.org/10.1109/TCAD.2016.2552822

2016 // Conference paper

On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation—A Case Study

Forum on Specification and Design Languages

Herdt, V.; Le, H.M.; Grobe, D.; Drechsler, R.

https://doi.org/10.1109/FDL.2016.7880375

2016 // Book

Parcoss: Efficient, parallelized, compiled symbolic simulation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Herdt, V.; Le, H.M.; Große, D.; Drechsler, R.

https://doi.org/10.1007/978-3-319-41540-6_10

2016 // Conference paper

Precise Error Determination of Approximated Components in Sequential Circuits Using Model Checking

Proceedings - Design Automation Conference

Chandrasekharan, A.; Soeken, M.; Große, D.; Drechsler, R.

https://doi.org/10.1145/2897937.2898069

2016 // Journal article

QMDDs: Efficient Quantum Function Representation and Manipulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Niemann, P.; Wille, R.; Miller, D.M.; Thornton, M.A.; Drechsler, R.

https://doi.org/10.1109/TCAD.2015.2459034

2016 // Conference paper

Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking

Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016

Gu, F.; Zhang, X.; Chen, M.; Große, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84973616996&partnerID=MN8TOARS

2016 // Conference paper

Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking

Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016

Gu, F.; Zhang, X.; Chen, M.; Gro{\ss}e, D.; Drechsler, R.

http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000382679200142&KeyUID=WOS:000382679200142

2016 // Conference paper

Rewriting HDL Descriptions for Line-Aware Synthesis of Reversible Circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Alwardi, Z.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2016.36

2016 // Book

Reversible and quantum circuits: Optimization and complexity analysis

Reversible and Quantum Circuits: Optimization and Complexity Analysis

Abdessaied, N.; Drechsler, R.

https://doi.org/10.1007/978-3-319-31937-7

2016 // Conference paper

Reversible computation

2015 6th International Conference on Green and Sustainable Computing

Drechsler, R.; Wille, R.

https://doi.org/10.1109/IGCC.2015.7393687

2016 // Journal article

Reversible synthesis of symmetric functions with a simple, regular structure and easy testability

ACM Journal on Emerging Technologies in Computing Systems

Deb, A.; Das, D.K.; Rahaman, H.; Wille, R.; Drechsler, R.; Bhattacharya, B.B.

https://doi.org/10.1145/2894757

2016 // Conference paper

Simulation graphs for reverse engineering

Proceedings of the 15th Conference on Formal Methods in Computer-Aided Design, FMCAD 2015

Soeken, M.; Sterin, B.; Drechsler, R.; Brayton, R.

https://doi.org/10.1109/FMCAD.2015.7542265

2016 // Journal article

SyReC: A hardware description language for the specification and synthesis of reversible circuits

Integration, the VLSI Journal

Wille, R.; Schönborn, E.; Soeken, M.; Drechsler, R.

https://doi.org/10.1016/j.vlsi.2015.10.001

2016 // Conference paper

Technology mapping of reversible circuits to Clifford+T quantum circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Abdessaied, N.; Amy, M.; Soeken, M.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2016.33

2016 // Journal article

Time-Resolved Detection of Diffusion-Limited Temperature Gradients Inside Single Isolated Burning Droplets Using Rainbow Refractometry

Combustion and Flame

Rosebrock, C.D.; Shirinzadeh, S.; Soeken, M.; Riefler, N.; Wriedt, T.; Drechsler, R.; Mädler, L.

https://doi.org/10.1016/j.combustflame.2016.03.007

2016 // Conference paper

Toward Formal Verification of Real-World SystemC TLM Peripheral Models—A Case Study

Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016

Le, H.M.; Herdt, V.; Gro{\ss}e, D.; Drechsler, R.

http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000382679200216&KeyUID=WOS:000382679200216

2016 // Conference paper

Toward Formal Verification of Real-World SystemC TLM Peripheral Models—A Case Study

Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016

Le, H.M.; Herdt, V.; Große, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84973661537&partnerID=MN8TOARS

2016 // Conference paper

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers

Proceedings of the European Test Workshop

Huhn, S.; Eggersgluss, S.; Drechsler, R.

https://doi.org/10.1109/ETS.2016.7519303

2015 // Conference paper

A Generic Representation of CCSL Time Constraints for UML/MARTE Models

Proceedings - Design Automation Conference

Peters, J.; Wille, R.; Przigoda, N.; Kühne, U.; Drechsler, R.

https://doi.org/10.1145/2744769.2744775

2015 // Conference paper

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization

Proceedings of The International Symposium on Multiple-Valued Logic

Deb, A.; Wille, R.; Drechsler, R.; Das, D.K.

https://doi.org/10.1109/ISMVL.2015.26

2015 // Conference paper

An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits

Proceedings of The International Symposium on Multiple-Valued Logic

Allahyari-Abhari, A.; Wille, R.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2015.25

2015 // Journal article

Analyzing SystemC Designs: SystemC Analysis Approaches for Various Applications

Sensors (Switzerland)

Stoppe, J.; Drechsler, R.

https://doi.org/10.3390/s150510399

2015 // Conference paper

Automated and quality-driven requirements engineering

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Drechsler, R.; Soeken, M.; Wille, R.

https://doi.org/10.1109/ICCAD.2014.7001410

2015 // Conference paper

Automated feature localization for dynamically generated SystemC designs

Proceedings -Design, Automation and Test in Europe, DATE

Stoppe, J.; Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84929347571&partnerID=MN8TOARS

2015 // Conference paper

Automated feature localization for dynamically generated SystemC designs

Proceedings -Design, Automation and Test in Europe, DATE

Stoppe, J.; Wille, R.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84929347571&partnerID=MN8TOARS

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Prof. Rolf Drechsler

Ecosystem

Publications

On Optimization-Based ATPG and Its Application to Highly Compacted Test Sets

On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation—A Case Study

Parcoss: Efficient, parallelized, compiled symbolic simulation

Precise Error Determination of Approximated Components in Sequential Circuits Using Model Checking

QMDDs: Efficient Quantum Function Representation and Manipulation

Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking

Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking

Rewriting HDL Descriptions for Line-Aware Synthesis of Reversible Circuits

Reversible and quantum circuits: Optimization and complexity analysis

Reversible computation

Reversible synthesis of symmetric functions with a simple, regular structure and easy testability

Simulation graphs for reverse engineering

SyReC: A hardware description language for the specification and synthesis of reversible circuits

Technology mapping of reversible circuits to Clifford+T quantum circuits

Time-Resolved Detection of Diffusion-Limited Temperature Gradients Inside Single Isolated Burning Droplets Using Rainbow Refractometry

Toward Formal Verification of Real-World SystemC TLM Peripheral Models—A Case Study

Toward Formal Verification of Real-World SystemC TLM Peripheral Models—A Case Study

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers

A Generic Representation of CCSL Time Constraints for UML/MARTE Models

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization

An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits

Analyzing SystemC Designs: SystemC Analysis Approaches for Various Applications

Automated and quality-driven requirements engineering

Automated feature localization for dynamically generated SystemC designs

Automated feature localization for dynamically generated SystemC designs

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions