2016 // Journal article
On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Eggersglüß, S.; Schmitz, K.; Krenz-Bååth, R.; Drechsler, R.
2016 // Conference paper
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation- A case study
Forum on Specification and Design Languages
Herdt, V.; Le, H.M.; Grobe, D.; Drechsler, R.
2016 // Book
Parcoss: Efficient parallelized compiled symbolic simulation
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Herdt, V.; Le, H.M.; Große, D.; Drechsler, R.
2016 // Conference paper
Precise error determination of approximated components in sequential circuits with model checking
Proceedings - Design Automation Conference
Chandrasekharan, A.; Soeken, M.; Große, D.; Drechsler, R.
2016 // Journal article
QMDDs: Efficient Quantum Function Representation and Manipulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Niemann, P.; Wille, R.; Miller, D.M.; Thornton, M.A.; Drechsler, R.
2016 // Conference paper
Quantitative timing analysis of UML activity diagrams using statistical model checking
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Gu, F.; Zhang, X.; Chen, M.; Große, D.; Drechsler, R.
2016 // Conference paper
Quantitative timing analysis of UML activity diagrams using statistical model checking
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Gu, F.; Zhang, X.; Chen, M.; Gro{\ss}e, D.; Drechsler, R.
2016 // Conference paper
Re-writing HDL descriptions for line-aware synthesis of reversible circuits
Proceedings of The International Symposium on Multiple-Valued Logic
Alwardi, Z.; Wille, R.; Drechsler, R.
2016 // Book
Reversible and quantum circuits: Optimization and complexity analysis
Reversible and Quantum Circuits: Optimization and Complexity Analysis
Abdessaied, N.; Drechsler, R.
2016 // Conference paper
Reversible computation
2015 6th International Green and Sustainable Computing Conference
Drechsler, R.; Wille, R.
2016 // Journal article
Reversible synthesis of symmetric functions with a simple regular structure and easy testability
ACM Journal on Emerging Technologies in Computing Systems
Deb, A.; Das, D.K.; Rahaman, H.; Wille, R.; Drechsler, R.; Bhattacharya, B.B.
2016 // Conference paper
Simulation graphs for reverse engineering
Proceedings of the 15th Conference on Formal Methods in Computer-Aided Design, FMCAD 2015
Soeken, M.; Sterin, B.; Drechsler, R.; Brayton, R.
2016 // Journal article
SyReC: A hardware description language for the specification and synthesis of reversible circuits
Integration, the VLSI Journal
Wille, R.; Schönborn, E.; Soeken, M.; Drechsler, R.
2016 // Conference paper
Technology mapping of reversible circuits to Clifford+T quantum circuits
Proceedings of The International Symposium on Multiple-Valued Logic
Abdessaied, N.; Amy, M.; Soeken, M.; Drechsler, R.
2016 // Journal article
Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry
Combustion and Flame
Rosebrock, C.D.; Shirinzadeh, S.; Soeken, M.; Riefler, N.; Wriedt, T.; Drechsler, R.; Mädler, L.
2016 // Conference paper
Towards formal verification of real-world SystemC TLM peripheral models - A case study
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Le, H.M.; Herdt, V.; Gro{\ss}e, D.; Drechsler, R.
2016 // Conference paper
Towards formal verification of real-world SystemC TLM peripheral models - A case study
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Le, H.M.; Herdt, V.; Große, D.; Drechsler, R.
2016 // Conference paper
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
Proceedings of the European Test Workshop
Huhn, S.; Eggersgluss, S.; Drechsler, R.
2015 // Conference paper
A generic representation of CCSL time constraints for UML/MARTE models
Proceedings - Design Automation Conference
Peters, J.; Wille, R.; Przigoda, N.; Kühne, U.; Drechsler, R.
2015 // Conference paper
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization
Proceedings of The International Symposium on Multiple-Valued Logic
Deb, A.; Wille, R.; Drechsler, R.; Das, D.K.
2015 // Conference paper
An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits
Proceedings of The International Symposium on Multiple-Valued Logic
Allahyari-Abhari, A.; Wille, R.; Drechsler, R.
2015 // Journal article
Analyzing systemC designs: SystemC analysis approaches for varying applications
Sensors (Switzerland)
Stoppe, J.; Drechsler, R.
2015 // Conference paper
Automated and quality-driven requirements engineering
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Drechsler, R.; Soeken, M.; Wille, R.
2015 // Conference paper
Automated feature localization for dynamically generated SystemC designs
Proceedings -Design, Automation and Test in Europe, DATE
Stoppe, J.; Wille, R.; Drechsler, R.
2015 // Conference paper
Automated feature localization for dynamically generated SystemC designs
Proceedings -Design, Automation and Test in Europe, DATE
Stoppe, J.; Wille, R.; Drechsler, R.
