2016 // Journal article
Complexity of reversible circuits and their quantum implementations
Theoretical Computer Science
Abdessaied, N.; Amy, M.; Drechsler, R.; Soeken, M.
2016 // Conference paper
Ensuring safety and reliability of IP-based system design-A container approach
Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP
Chandrasekharan, A.; Schmitz, K.; Kuhne, U.; Drechsler, R.
2016 // Conference paper
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Shirinzadeh, S.; Soeken, M.; Gaillardon, P.-E.; Drechsler, R.
2016 // Conference paper
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Shirinzadeh, S.; Soeken, M.; Gaillardon, P.-E.; Drechsler, R.
2016 // Conference paper
Fault detection in parity preserving reversible circuits
Proceedings of The International Symposium on Multiple-Valued Logic
Przigoda, N.; Dueck, G.; Wille, R.; Drechsler, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Conference paper
Formal methods for emerging technologies
2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
Wille, R.; Drechsler, R.
2016 // Conference paper
Formal verification of integer multipliers by combining Gr{\"o}bner basis with logic reduction
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Sayed-Ahmed, A.; Gro{\ss}e, D.; K{\" u}hne, U.; Soeken, M.; Drechsler, R.
2016 // Conference paper
Formal verification of integer multipliers by combining Gröbner basis with logic reduction
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
Sayed-Ahmed, A.; Große, D.; Kühne, U.; Soeken, M.; Drechsler, R.
2016 // Conference paper
Frame conditions in symbolic representations of UML/OCL models
2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2016
Przigoda, N.; Filho, J.G.; Niemann, P.; Wille, R.; Drechsler, R.
2016 // Conference paper
From biochips to quantum circuits: Computer-aided design for emerging technologies
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Wille, R.; Li, B.; Schlichtmann, U.; Drechsler, R.
2016 // Journal article
Gates vs. splitters: Contradictory optimization objectives in the synthesis of optical circuits
ACM Journal on Emerging Technologies in Computing Systems
Deb, A.; Wille, R.; Keszoöcze, O.; Hillmich, S.; Drechsler, R.
2016 // Conference paper
Ground setting properties for an efficient translation of OCL in SMT-based model finding
Proceedings - 19th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, MODELS 2016
Przigoda, N.; Willezy, R.; Drechsler, R.
2016 // Conference paper
Guided lightweight Software test qualification for IP integration using Virtual Prototypes
Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
Große, D.; Le, H.M.; Hassan, M.; Drechsler, R.
2016 // Conference paper
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC
Proceedings of the IEEE International Conference on VLSI Design
Drechsler, R.; Stoppe, J.
2016 // Conference paper
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
Proceedings of the IEEE International Conference on VLSI Design
Biswal, L.; Bandyopadhyay, C.; Wille, R.; Drechsler, R.; Rahaman, H.
2016 // Book
Initial ideas for automatic design and verification of control logic in reversible HDLs work in progress report
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Wille, R.; Keszocze, O.; Othmer, L.; Thomsen, M.K.; Drechsler, R.
2016 // Conference paper
Integrating an SMT-based ModelFinder into USE
CEUR Workshop Proceedings
Przigoda, N.; Hilken, F.; Peters, J.; Wille, R.; Gogolla, M.; Drechsler, R.
2016 // Conference paper
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Wille, R.; Keszocze, O.; Walter, M.; Rohrs, P.; Chattopadhyay, A.; Drechsler, R.
2016 // Conference paper
Multi-objective BDD optimization for RRAM based circuit design
Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016
Shirinzadeh, S.; Soeken, M.; Drechsler, R.
2016 // Conference paper
Nearest-neighbor and fault-tolerant quantum circuit implementation
Proceedings of The International Symposium on Multiple-Valued Logic
Biswal, L.; Bandyopadhyay, C.; Chattopadhyay, A.; Wille, R.; Drechsler, R.; Rahaman, H.
