2016 // Journal article
Complexity of Reversible Circuits and Their Quantum Implementations
Theoretical Computer Science
Abdessaied, N.; Amy, M.; Drechsler, R.; Soeken, M.
2016 // Conference paper
Ensuring the Safety and Reliability of IP-Based System Design: A Container Approach
Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP
Chandrasekharan, A.; Schmitz, K.; Kuhne, U.; Drechsler, R.
2016 // Conference paper
Fast Logic Synthesis for RRAM-Based In-Memory Computing Using Majority-Inverter Graphs
Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016
Shirinzadeh, S.; Soeken, M.; Gaillardon, P.-E.; Drechsler, R.
2016 // Conference paper
Fast Logic Synthesis for RRAM-Based In-Memory Computing Using Majority-Inverter Graphs
Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016
Shirinzadeh, S.; Soeken, M.; Gaillardon, P.-E.; Drechsler, R.
2016 // Conference paper
Fault Detection in Parity-Preserving Reversible Circuits
Proceedings of The International Symposium on Multiple-Valued Logic
Przigoda, N.; Dueck, G.; Wille, R.; Drechsler, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Book
Foreword
Lecture Notes in Electrical Engineering
Drechsler, R.; Wille, R.
2016 // Conference paper
Formal Methods for Emerging Technologies
2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
Wille, R.; Drechsler, R.
2016 // Conference paper
Formal Verification of Integer Multipliers by Combining Gröbner Bases with Logic Reduction
Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016
Sayed-Ahmed, A.; Gro{\ss}e, D.; K{\" u}hne, U.; Soeken, M.; Drechsler, R.
2016 // Conference paper
Formal Verification of Integer Multipliers by Combining Gröbner Bases with Logic Reduction
Proceedings of the 2016 Design, Automation, and Test in Europe Conference and Exhibition, DATE 2016
Sayed-Ahmed, A.; Große, D.; Kühne, U.; Soeken, M.; Drechsler, R.
2016 // Conference paper
Frame conditions in symbolic representations of UML/OCL models
2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2016
Przigoda, N.; Filho, J.G.; Niemann, P.; Wille, R.; Drechsler, R.
2016 // Conference paper
From Biochips to Quantum Circuits: Computer-Aided Design for Emerging Technologies
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Wille, R.; Li, B.; Schlichtmann, U.; Drechsler, R.
2016 // Journal article
Gates vs. Splitters: Conflicting Optimization Objectives in the Synthesis of Optical Circuits
ACM Journal on Emerging Technologies in Computing Systems
Deb, A.; Wille, R.; Keszoöcze, O.; Hillmich, S.; Drechsler, R.
2016 // Conference paper
Ground-setting properties for an efficient translation of OCL in SMT-based model finding
Proceedings - 19th ACM/IEEE International Conference on Model-Driven Engineering Languages and Systems, MODELS 2016
Przigoda, N.; Willezy, R.; Drechsler, R.
2016 // Conference paper
Guided, Lightweight Software Test Qualification for IP Integration Using Virtual Prototypes
Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016
Große, D.; Le, H.M.; Hassan, M.; Drechsler, R.
2016 // Conference paper
Hardware/Software Co-Visualization at the Electronic System Level Using SystemC
Proceedings of the IEEE International Conference on VLSI Design
Drechsler, R.; Stoppe, J.
2016 // Conference paper
Improving the Implementation of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
Proceedings of the IEEE International Conference on VLSI Design
Biswal, L.; Bandyopadhyay, C.; Wille, R.; Drechsler, R.; Rahaman, H.
2016 // Book
Initial Ideas for the Automatic Design and Verification of Control Logic in Reversible HDLs: Work in Progress Report
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Wille, R.; Keszocze, O.; Othmer, L.; Thomsen, M.K.; Drechsler, R.
2016 // Conference paper
Integrating an SMT-based ModelFinder into USE
CEUR Workshop Proceedings
Przigoda, N.; Hilken, F.; Peters, J.; Wille, R.; Gogolla, M.; Drechsler, R.
2016 // Conference paper
Look-ahead schemes for nearest-neighbor optimization of 1D and 2D quantum circuits
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Wille, R.; Keszocze, O.; Walter, M.; Rohrs, P.; Chattopadhyay, A.; Drechsler, R.
2016 // Conference paper
Multi-objective BDD optimization for RRAM-based circuit design
Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016
Shirinzadeh, S.; Soeken, M.; Drechsler, R.
2016 // Conference paper
Nearest-neighbor and fault-tolerant quantum circuit implementation
Proceedings of The International Symposium on Multiple-Valued Logic
Biswal, L.; Bandyopadhyay, C.; Chattopadhyay, A.; Wille, R.; Drechsler, R.; Rahaman, H.
