Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

2004 // Journal article

Method for Constructing Recursive Algorithms for Calculating Reed-Muller-Fourier Polarity Matrices

Journal of Multiple-Valued Logic and Soft Computing

Jankovic, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-3142707555&partnerID=MN8TOARS

2004 // Conference paper

Minimization of the expected path length in BDDs based on local changes

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Ebendt, R.; Günther, W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-2442624433&partnerID=MN8TOARS

2004 // Conference paper

Placement and Routing Optimization for Circuits Derived from BDDS

Proceedings - IEEE International Symposium on Circuits and Systems

Eschbach, T.; Drechsler, R.; Becker, B.

http://www.scopus.com/inward/record.url?eid=2-s2.0-4344671863&partnerID=MN8TOARS

2004 // Conference paper

Reduction of the Size of Multi-Valued Decision Diagrams Using Copy Properties

Proceedings of The International Symposium on Multiple-Valued Logic

Janković, D.; Stanković, R.S.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-3142730834&partnerID=MN8TOARS

2004 // Journal article

Synthesis of Fully Testable Circuits from BDDs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Drechsler, R.; Shi, J.; Fey, G.

https://doi.org/10.1109/TCAD.2004.823342

2004 // Conference paper

Toward Formal Verification at the System Level

Proceedings of the International Workshop on Rapid System Prototyping

Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-4944249662&partnerID=MN8TOARS

2004 // Journal article

Using Word-Level Information in Formal Hardware Verification

Automation and Telemechanics

Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-4344614451&partnerID=MN8TOARS

2004 // Journal article

Using Word-Level Information in Formal Hardware Verification

Automation and Remote Control

Drechsler, R.

https://doi.org/10.1023/B:AURC.0000030907.28679.82

2003 // Journal article

An Approach to Formal Verification of Circuits in SystemC, An Approach to Formal Verification of Circuit Descriptions in SystemC

IT - Information Technology

Große, D.; Drechsler, R.

https://doi.org/10.1524/itit.45.4.219.22731

2003 // Journal article

An Improved Branch-and-Bound Algorithm for Exact BDD Minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Ebendt, R.; Günther, W.; Drechsler, R.

https://doi.org/10.1109/TCAD.2003.819427

2003 // Conference paper

Augmented sifting of multi-valued decision diagrams

Proceedings of The International Symposium on Multiple-Valued Logic

Miller, D.M.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0037481739&partnerID=MN8TOARS

2003 // Conference paper

BDD-Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability

Proceedings of the Asian Test Symposium

Shi, J.; Fey, G.; Drechsler, R.

https://doi.org/10.1109/ATS.2003.1250825

2003 // Conference paper

BDD-based verification of scalable designs

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Große, D.; Drechsler, R.

https://doi.org/10.1109/HLDVT.2003.1252485

2003 // Conference paper

Combination of Lower Bounds in Exact BDD Minimization

Proceedings -Design, Automation and Test in Europe, DATE

Ebendt, R.; Gunther, W.; Drechsler, R.

https://doi.org/10.1109/DATE.2003.1253698

2003 // Journal article

Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams

IEEE Transactions on Computers

Günther, W.; Drechsler, R.

https://doi.org/10.1109/TC.2003.1228514

2003 // Conference paper

Efficient Minimization of Multiple-Valued Decision Diagrams for Incompletely Specified Functions

Proceedings of The International Symposium on Multiple-Valued Logic

Popel, D.V.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0038157036&partnerID=MN8TOARS

2003 // Journal article

Exact routing with search space reduction

IEEE Transactions on Computers

Schmiedle, F.; Drechsler, R.; Becker, B.

https://doi.org/10.1109/TC.2003.1204836

2003 // Conference paper

Fast heuristics for edge coloring of large graphs

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Hilgemeier, M.; Drechsler, N.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84873321866&partnerID=MN8TOARS

2003 // Conference paper

Formal Verification of LTL Formulas for SystemC Designs

Proceedings - IEEE International Symposium on Circuits and Systems

Große, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0038082058&partnerID=MN8TOARS

2003 // Book

GAME-HDL: Implementation of evolutionary algorithms using hardware description languages

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, R.; Drechsler, N.

http://www.scopus.com/inward/record.url?eid=2-s2.0-35248832557&partnerID=MN8TOARS

2003 // Conference paper

Minimization of Transitions through Complementation and Resequencing Using Evolutionary Algorithms

IASTED International Multi-Conference on Applied Informatics

Drechsler, R.; Drechsler, N.

http://www.scopus.com/inward/record.url?eid=2-s2.0-1442277886&partnerID=MN8TOARS

2003 // Conference paper

Minimizing the Number of One-Paths in BDDs Using an Evolutionary Algorithm

2003 Congress on Evolutionary Computation, CEC 2003 - Proceedings

Hilgemeier, M.; Drechsler, N.; Drechsler, R.

https://doi.org/10.1109/CEC.2003.1299881

2003 // Conference paper

Modeling Multi-Valued Circuits in SystemC

Proceedings of The International Symposium on Multiple-Valued Logic

Große, D.; Fey, G.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0038495617&partnerID=MN8TOARS

2003 // Conference paper

MuTaTe: An Efficient Design-for-Testability Technique for Multiplexer-Based Circuits

Proceedings of the IEEE Great Lakes Symposium on VLSI

Drechsler, R.; Shi, J.; Fey, G.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0037699728&partnerID=MN8TOARS

2003 // Journal article

Recursive bipartitioning of netlists for a large number of partitions

Journal of Systems Architecture

Drechsler, R.; Günther, W.; Eschbach, T.; Linhard, L.; Angst, G.

https://doi.org/10.1016/S1383-7621(03)00093-6

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Prof. Rolf Drechsler

Ecosystem

Publications

Method for Constructing Recursive Algorithms for Calculating Reed-Muller-Fourier Polarity Matrices

Minimization of the expected path length in BDDs based on local changes

Placement and Routing Optimization for Circuits Derived from BDDS

Reduction of the Size of Multi-Valued Decision Diagrams Using Copy Properties

Synthesis of Fully Testable Circuits from BDDs

Toward Formal Verification at the System Level

Using Word-Level Information in Formal Hardware Verification

Using Word-Level Information in Formal Hardware Verification

An Approach to Formal Verification of Circuits in SystemC, An Approach to Formal Verification of Circuit Descriptions in SystemC

An Improved Branch-and-Bound Algorithm for Exact BDD Minimization

Augmented sifting of multi-valued decision diagrams

BDD-Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability

BDD-based verification of scalable designs

Combination of Lower Bounds in Exact BDD Minimization

Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams

Efficient Minimization of Multiple-Valued Decision Diagrams for Incompletely Specified Functions

Exact routing with search space reduction

Fast heuristics for edge coloring of large graphs

Formal Verification of LTL Formulas for SystemC Designs

GAME-HDL: Implementation of evolutionary algorithms using hardware description languages

Minimization of Transitions through Complementation and Resequencing Using Evolutionary Algorithms

Minimizing the Number of One-Paths in BDDs Using an Evolutionary Algorithm

Modeling Multi-Valued Circuits in SystemC

MuTaTe: An Efficient Design-for-Testability Technique for Multiplexer-Based Circuits

Recursive bipartitioning of netlists for a large number of partitions

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions