2004 // Journal article
Method for construction of recursive algorithms for Reed-Muller-Fourier polarity matrices calculation
Journal of Multiple-Valued Logic and Soft Computing
Jankovic, D.; Drechsler, R.
2004 // Conference paper
Minimization of the expected path length in BDDs based on local changes
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Ebendt, R.; Günther, W.; Drechsler, R.
2004 // Conference paper
Placement and routing optimization for circuits derived from BDDS
Proceedings - IEEE International Symposium on Circuits and Systems
Eschbach, T.; Drechsler, R.; Becker, B.
2004 // Conference paper
Reduction of sizes of multi-valued decision diagrams by copy properties
Proceedings of The International Symposium on Multiple-Valued Logic
Janković, D.; Stanković, R.S.; Drechsler, R.
2004 // Journal article
Synthesis of Fully Testable Circuits From BDDs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Drechsler, R.; Shi, J.; Fey, G.
2004 // Conference paper
Towards formal verification on the system level
Proceedings of the International Workshop on Rapid System Prototyping
Drechsler, R.
2004 // Journal article
Using word-level information in formal hardware verification
Avtomatika i Telemekhanika
Drechsler, R.
2004 // Journal article
Using word-level information in formal hardware verification
Automation and Remote Control
Drechsler, R.
2003 // Journal article
An approach for formal verification of circuits in SystemC,Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
IT - Information Technology
Große, D.; Drechsler, R.
2003 // Journal article
An Improved Branch and Bound Algorithm for Exact BDD Minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ebendt, R.; Günther, W.; Drechsler, R.
2003 // Conference paper
Augmented sifting of multiple-valued decision diagrams
Proceedings of The International Symposium on Multiple-Valued Logic
Miller, D.M.; Drechsler, R.
2003 // Conference paper
BDD based synthesis of symmetric functions with full path-delay fault testability
Proceedings of the Asian Test Symposium
Shi, J.; Fey, G.; Drechsler, R.
2003 // Conference paper
BDD-based verification of scalable designs
Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
Große, D.; Drechsler, R.
2003 // Conference paper
Combination of lower bounds in exact BDD minimization
Proceedings -Design, Automation and Test in Europe, DATE
Ebendt, R.; Gunther, W.; Drechsler, R.
2003 // Journal article
Efficient minimization and manipulation of linearly transformed binary decision diagrams
IEEE Transactions on Computers
Günther, W.; Drechsler, R.
2003 // Conference paper
Efficient minimization of multiple-valued decision diagrams for incompletely specified functions
Proceedings of The International Symposium on Multiple-Valued Logic
Popel, D.V.; Drechsler, R.
2003 // Journal article
Exact routing with search space reduction
IEEE Transactions on Computers
Schmiedle, F.; Drechsler, R.; Becker, B.
2003 // Conference paper
Fast heuristics for the edge coloring of large graphs
Proceedings - Euromicro Symposium on Digital System Design, DSD 2003
Hilgemeier, M.; Drechsler, N.; Drechsler, R.
2003 // Conference paper
Formal verification of LTL formulas for systemc designs
Proceedings - IEEE International Symposium on Circuits and Systems
Große, D.; Drechsler, R.
2003 // Book
GAME-HDL: Implementation of evolutionary algorithms using hardware description languages
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Drechsler, R.; Drechsler, N.
2003 // Conference paper
Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms
IASTED International Multi-Conference on Applied Informatics
Drechsler, R.; Drechsler, N.
2003 // Conference paper
Minimizing the number of one-paths in BDDs by an evolutionary algorithm
2003 Congress on Evolutionary Computation, CEC 2003 - Proceedings
Hilgemeier, M.; Drechsler, N.; Drechsler, R.
2003 // Conference paper
Modeling multi-valued circuits in systemC
Proceedings of The International Symposium on Multiple-Valued Logic
Große, D.; Fey, G.; Drechsler, R.
2003 // Conference paper
MuTaTe: An efficient design for testability technique for multiplexor based circuits
Proceedings of the IEEE Great Lakes Symposium on VLSI
Drechsler, R.; Shi, J.; Fey, G.
2003 // Journal article
Recursive bi-partitioning of netlists for large number of partitions
Journal of Systems Architecture
Drechsler, R.; Günther, W.; Eschbach, T.; Linhard, L.; Angst, G.
