2005 // Conference paper
Checksyc: An efficient property checker for RTL systemc designs
Proceedings - IEEE International Symposium on Circuits and Systems
Große, D.; Drechsler, R.
2005 // Journal article
Combining ordered best-first search with branch and bound for exact BDD minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ebendt, R.; Günther, W.; Drechsler, R.
2005 // Conference paper
Controlling the memory during manipulation of word-level decision diagrams
Proceedings of The International Symposium on Multiple-Valued Logic
Kinder, S.; Fey, G.; Drechsler, R.
2005 // Conference paper
Debugging sequential circuits using boolean satisfiability
Proceedings - International Workshop on Microprocessor Test and Verification
Ali, M.F.; Veneris, A.; Safarpour, S.; Abadir, M.; Drechsler, R.; Smith, A.
2005 // Conference paper
Experimental studies on SAT-based test pattern generation for industrial circuits
ASICON 2005: 2005 6th International Conference on ASIC, Proceedings
Shi, J.; Fey, G.; Drechsler, R.; Glowatz, A.; Schlöffel, J.; Hapke, F.
2005 // Conference paper
Formal verification of the instruction set of a modeled microprocessor in SystemC,Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
INFORMATIK 2005 - Informatik LIVE!, Beitrage der 35. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)
Große, D.; Kühne, U.; Drechsler, R.
2005 // Journal article
Generic implementation of multi-valued logic decision diagram packages
Journal of Multiple-Valued Logic and Soft Computing
Drechsler, R.; Janković, D.; Stanković, R.S.
2005 // Conference paper
HW/SW co-verification of a RISC CPU using bounded model checking
Proceedings - International Workshop on Microprocessor Test and Verification
Große, D.; Kühne, U.; Drechsler, R.
2005 // Conference paper
Lecture Notes in Computer Science: Preface
Lecture Notes in Computer Science
Rothlauf, F.; Corne, D.W.; Machado, P.; Smith, G.D.; Branke, J.; Drechsler, R.; Marchior, E.; Squillero, G.; Cagnoni, S.; Jin, Y.; Romero, J.
2005 // Conference paper
Lower bounds for dynamic BDD reordering
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Ebendt, R.; Drechsler, R.
2005 // Conference paper
PASSAT: Efficient SAT-based test pattern generation for industrial circuits
Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI
Shi, J.; Fey, G.; Drechsler, R.; Glowatz, A.; Hapke, F.; Schlöffel, J.
2005 // Conference paper
Post-verification debugging of hierarchical designs
Proceedings - International Workshop on Microprocessor Test and Verification
Ali, M.F.; Safarpour, S.; Veneris, A.; Abadir, M.S.; Drechsler, R.
2005 // Conference paper
Post-verification debugging of hierarchical designs
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Ali, M.F.; Safarpour, S.; Veneris, A.; Abadir, M.S.; Drechsler, R.
2005 // Conference paper
Quasi-exact BDD minimization using relaxed best-first search
Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI
Ebendt, R.; Drechsler, R.
2005 // Conference paper
SyCE: An integrated environment for system design in systemC
Proceedings of the International Workshop on Rapid System Prototyping
Drechsler, R.; Fey, G.; Genz, C.; Große, D.
2005 // Conference paper
System level validation using formal techniques
IEE Proceedings: Computers and Digital Techniques
Drechsler, R.; Große, D.
2005 // Conference paper
Utilizing don't care states in SAT-based bounded sequential problems
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Safarpour, S.; Veneris, A.; Fey, G.; Drechsler, R.
2004 // Conference paper
Algorithms for Taylor expansion diagrams
Proceedings of The International Symposium on Multiple-Valued Logic
Fey, G.; Drechsler, R.; Ciesielski, M.
2004 // Conference paper
BDD circuit optimization for path delay fault testability
Proceedings of the EUROMICRO Systems on Digital System Design, DSD 2004
Fey, G.; Shi, J.; Drechsler, R.
2004 // Conference paper
Checkers for SystemC designs
Proceedings - 2nd ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE'04
Große, D.; Drechsler, R.
2004 // Conference paper
Combining ordered best-first search with branch and bound for exact BDD minimization
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Ebendt, R.; Günther, W.; Drechsler, R.
2004 // Conference paper
Debugging sequential circuits using Boolean satisfiability
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Ali, M.F.; Veneris, A.; Safarpour, S.; Drechsler, R.; Smith, A.; Abadir, M.
2004 // Book
Disjoint sum of product minimization by evolutionary algorithms
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Drechsler, N.; Hilgemeier, M.; Fey, G.; Drechsler, R.
2004 // Conference paper
Improving simulation-based verification by means of formal methods
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Fey, G.; Drechsler, R.
2004 // Conference paper
Managing don't cares in boolean satisfiability
Proceedings - Design, Automation and Test in Europe Conference and Exhibition
Safarpour, S.; Veneris, A.; Drechsler, R.; Lee, J.
