2006 // Conference paper
An integrated approach for combining BDD and SAT provers
Proceedings of the IEEE International Conference on VLSI Design
Drechsler, R.; Fey, G.; Kinder, S.
2006 // Book
Automatic test pattern generation
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Drechsler, R.; Fey, G.
2006 // Conference paper
Avoiding false negatives in formal verification for protocol-driven blocks
Proceedings -Design, Automation and Test in Europe, DATE
Fey, G.; Große, D.; Drechsler, R.
2006 // Conference paper
Complete formal verification of multi core embedded systems using bounded model checking
2006 IEEE Dallas/CAS Workshop onDesign, Applications, Integration and Software, DCAS-06
Kühne, U.; Große, D.; Drechsler, R.
2006 // Journal article
Effect of improved lower bounds in dynamic BDD reordering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ebendt, R.; Drechsler, R.
2006 // Conference paper
Efficiency of multi-valued encoding in SAT-based ATPG
Proceedings of The International Symposium on Multiple-Valued Logic
Fey, G.; Shi, J.; Drechsler, R.
2006 // Book
Efficient evolutionary approaches for the data ordering problem with inversion
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Logofatu, D.; Drechsler, R.
2006 // Conference paper
Efficient minimization of fully testable 2-SPP networks
Proceedings -Design, Automation and Test in Europe, DATE
Bernasconi, A.; Ciriani, V.; Drechsler, R.; Villa, T.
2006 // Journal article
Exact minimisation of path-related objective functions for binary decision diagrams
IEE Proceedings: Computers and Digital Techniques
Ebendt, R.; Drechsler, R.
2006 // Conference paper
Exact toffoli network synthesis of reversible logic using boolean satisfiability
2006 IEEE Dallas/CAS Workshop onDesign, Applications, Integration and Software, DCAS-06
Große, D.; Chen, X.; Drechsler, R.
2006 // Book
Exploration of sequential depth by evolutionary algorithms
IFIP International Federation for Information Processing
Drechsler, N.; Drechsler, R.
2006 // Conference paper
HW/SW co-verification of embedded systems using bounded model checking
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Große, D.; Kühne, U.; Drechsler, R.
2006 // Conference paper
Integrating observability don't cares in all-solution SAT solvers
Proceedings - IEEE International Symposium on Circuits and Systems
Safarpour, S.; Veneris, A.; Drechsler, R.
2006 // Book
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): Preface
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Rothlauf, F.; Costa, E.; Lutton, E.; Romero, J.; Takagi, H.; Branke, J.; Cotta, C.; Machado, P.; Smith, G.D.; Cagnoni, S.; Drechsler, R.; Moore, J.H.; Squillero, G.
2006 // Journal article
Minimizing the number of paths in BDDs: Theory and algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fey, G.; Drechsler, R.
2006 // Conference paper
On the relation between simulation-based and SAT-based diagnosis
Proceedings -Design, Automation and Test in Europe, DATE
Fey, G.; Safarpour, S.; Veneris, A.; Drechsler, R.
2006 // Conference paper
On the sensitivity of BDDs with respect to path-related objective functions
Proceedings - IEEE International Symposium on Circuits and Systems
Ebendt, R.; Drechsler, R.
2006 // Book
Stuck-at-fault testability of SPP three-level logic forms
IFIP International Federation for Information Processing
Ciriani, V.; Bernasconi, A.; Drechsler, R.
2006 // Conference paper
System exploration of SystemC designs
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Genz, C.; Drechsler, R.
2006 // Book
System-level validation using formal techniques
System-on-Chip: Next Generation Electronics
Drechsler, R.; Große, D.
2006 // Conference paper
Technical documentation of software and hardware in embedded systems
IFIP VLSI-SoIC 2006 - IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip
Muranko, B.; Drechsler, R.
2006 // Journal article
Testability of SPP three-level logic networks in static fault models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Ciriani, V.; Bemasconi, A.; Drechsler, R.
2005 // Book
Acceleration of SAT-based iterative property checking
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Große, D.; Drechsler, R.
2005 // Book
Advanced BDD optimization
Advanced BDD Optimization
Ebendt, R.; Fey, G.; Drechsler, R.
2005 // Conference paper
Bridging fault testability of BDD circuits
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Shi, J.; Fey, G.; Drechsler, R.
