Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

2003 // Conference paper

Synthesizing checkers for online verification of system-on-chip designs

Proceedings - IEEE International Symposium on Circuits and Systems

Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0038080942&partnerID=MN8TOARS

2003 // Conference paper

Using games for benchmarking and representing the entire solution space using symbolic techniques

Proceedings of The International Symposium on Multiple-Valued Logic

Fey, G.; Kinder, S.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0037481743&partnerID=MN8TOARS

2002 // Journal article

A Genetic Algorithm for Minimizing OPKFDDs

IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences

Jung, M.; Lee, G.; Park, S.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0037004709&partnerID=MN8TOARS

2002 // Conference paper

Computing Walsh, arithmetic, and Reed-Muller spectral decision diagrams using graph transformations

GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Townsend, W.J.; Thornton, M.A.; Drechsler, R.; Miller, D.M.

https://doi.org/10.1145/505306.505344

2002 // Book

Crossing Reduction Through Window Optimization

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Eschbach, T.; Günther, W.; Drechsler, R.; Becker, B.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84867472695&partnerID=MN8TOARS

2002 // Conference paper

Optimization of decision diagrams using copy properties

Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods, and Tools, DSD 2002

Jankovic, D.; Stankovic, R.S.; Drechsler, R.

https://doi.org/10.1109/DSD.2002.1115374

2002 // Journal article

Efficient Algorithms for Creating Linearly Independent Decision Diagrams and Mapping Them to Regular Layouts

VLSI Design

Perkowski, M.; Falkowski, B.; Chrzanowska-Jeske, M.; Drechsler, R.

https://doi.org/10.1080/10655140290009792

2002 // Journal article

Efficient Computation of Fixed-Polarity Polynomial Expressions for Multi-valued Logic Functions

Proceedings of The International Symposium on Multiple-Valued Logic

Janković, D.; Stanković, R.S.; Drechsler, R.

https://doi.org/10.1109/ISMVL.2002.1011073

2002 // Conference paper

Evaluation of Static Variable Ordering Heuristics for MDD Construction

Proceedings of The International Symposium on Multiple-Valued Logic

Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0036088869&partnerID=MN8TOARS

2002 // Journal article

Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs

VLSI Design

Thornton, M.A.; Drechsler, R.; Günther, W.

https://doi.org/10.1080/10655140290009800

2002 // Journal article

Low-power optimization techniques for BDD-mapped circuits using temporal correlation

Canadian Journal of Electrical and Computer Engineering

Drechsler, R.; Kerttu, M.; Lindgren, P.; Thornton, M.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0036822953&partnerID=MN8TOARS

2002 // Journal article

Minimization of Free BDDs

Integration, the VLSI Journal

Günther, W.; Drechsler, R.

https://doi.org/10.1016/S0167-9260(02)00041-X

2002 // Journal article

Minimization of Word-Level Decision Diagrams

Integration, the VLSI Journal

Drechsler, R.; Günther, W.; Höreth, S.

https://doi.org/10.1016/S0167-9260(02)00047-0

2002 // Conference paper

Minimizing the Number of Paths in BDDs

Proceedings - 15th Symposium on Integrated Circuits and Systems Design, SBCCI 2002

Fey, G.; Drechsler, R.

https://doi.org/10.1109/SBCCI.2002.1137683

2002 // Conference paper

Multi-output timed Shannon circuits

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Thornton, M.A.; Drechsler, R.; Miller, D.M.

https://doi.org/10.1109/ISVLSI.2002.1016873

2002 // Conference paper

On the Construction of Multiple-Valued Decision Diagrams

Proceedings of The International Symposium on Multiple-Valued Logic

Miller, D.M.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0036080140&partnerID=MN8TOARS

2002 // Conference paper

On the Relationship Between SAT and BDDs for Equivalence Checking

Proceedings - International Symposium on Quality Electronic Design, ISQED

Reda, S.; Drechsler, R.; Orailoglu, A.

https://doi.org/10.1109/ISQED.2002.996778

2002 // Conference paper

Reachability Analysis for Formal Verification of SystemC

Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods, and Tools, DSD 2002

Drechsler, R.; Grosse, D.

https://doi.org/10.1109/DSD.2002.1115387

2002 // Conference paper

Recursive bipartitioning of netlists for a large number of partitions

Proceedings - Euromicro Symposium on Digital System Design: Architectures, Methods, and Tools, DSD 2002

Drechsler, R.; Gunther, W.; Eschbach, T.; Linhard, L.; Angst, G.

https://doi.org/10.1109/DSD.2002.1115349

2002 // Conference paper

RTL data path verification using integer linear programming

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Brinkmann, R.; Drechsler, R.

https://doi.org/10.1109/ASPDAC.2002.995022

2002 // Journal article

Estimation of Switching Activity in Finite-State Machines for Low-Power Synthesis

Proceedings - IEEE International Symposium on Circuits and Systems

Kerttu, M.; Lindgren, P.; Thornton, M.; Drechsler, R.

https://doi.org/10.1109/ISCAS.2002.1010389

2002 // Conference paper

Using BDDs for Disjoint SOP Minimization

Midwest Symposium on Circuits and Systems

Fey, G.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0036979279&partnerID=MN8TOARS

2002 // Journal article

Verifying the Integrity of Decision Diagrams

Integration, the VLSI Journal

Drechsler, R.

https://doi.org/10.1016/S0167-9260(02)00042-1

2001 // Conference paper

Application of a Hardware Synthesis Technique for Database Query Optimization

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Komaragiri, V.; Thornton, M.A.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0034770584&partnerID=MN8TOARS

2001 // Journal article

Binary Decision Diagrams: Theory and Practice

International Journal on Software Tools for Technology Transfer

Drechsler, R.; Sieling, D.

https://doi.org/10.1007/s100090100056

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Prof. Rolf Drechsler

Ecosystem

Publications

Synthesizing checkers for online verification of system-on-chip designs

Using games for benchmarking and representing the entire solution space using symbolic techniques

A Genetic Algorithm for Minimizing OPKFDDs

Computing Walsh, arithmetic, and Reed-Muller spectral decision diagrams using graph transformations

Crossing Reduction Through Window Optimization

Optimization of decision diagrams using copy properties

Efficient Algorithms for Creating Linearly Independent Decision Diagrams and Mapping Them to Regular Layouts

Efficient Computation of Fixed-Polarity Polynomial Expressions for Multi-valued Logic Functions

Evaluation of Static Variable Ordering Heuristics for MDD Construction

Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs

Low-power optimization techniques for BDD-mapped circuits using temporal correlation

Minimization of Free BDDs

Minimization of Word-Level Decision Diagrams

Minimizing the Number of Paths in BDDs

Multi-output timed Shannon circuits

On the Construction of Multiple-Valued Decision Diagrams

On the Relationship Between SAT and BDDs for Equivalence Checking

Reachability Analysis for Formal Verification of SystemC

Recursive bipartitioning of netlists for a large number of partitions

RTL data path verification using integer linear programming

Estimation of Switching Activity in Finite-State Machines for Low-Power Synthesis

Using BDDs for Disjoint SOP Minimization

Verifying the Integrity of Decision Diagrams

Application of a Hardware Synthesis Technique for Database Query Optimization

Binary Decision Diagrams: Theory and Practice

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions