Prof. Rolf Drechsler

Further information:

AG Computer Architecture & Reliable Embedded Systems; DFKI Cyber Physical Systems

Ecosystem

Member of the Board of Directors of the research focus "Minds, Media, Machines"

Head of the Computer Architecture working group

Director of the Cyber Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI)

Co-founder and speaker of the Data Science Center (DSC) at the University of Bremen

Dean of Faculty 3 Mathematics/Computer Science

Supervisor for the research training group "CAUSE"

Member of the CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Member of the Board of Directors of the "Logdynamics" research cluster

Publications

1999 // Book

Multi-objective Optimization in Evolutionary Algorithms Using Satisfiability Classes

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, N.; Drechsler, R.; Becker, B.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84937399878&partnerID=MN8TOARS

1999 // Journal article

OKFDD Minimization Using Genetic Algorithms with Application to Circuit Design

Integration, the VLSI Journal

Drechsler, R.; Becker, B.; Drechsler, N.

https://doi.org/10.1016/S0167-9260(99)00017-6

1999 // Conference paper

Power Consumption in XOR-Based Circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Kaushik Roy, Y.Y.; Drechsler, R.

https://doi.org/10.1109/ASPDAC.1999.760018

1999 // Conference paper

Probabilistic IP Verification

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Drechsler, Rolf; Becker, Bernd

http://www.scopus.com/inward/record.url?eid=2-s2.0-0033327304&partnerID=MN8TOARS

1999 // Journal article

Pseudo-Kronecker Expressions for Symmetric Functions

IEEE Transactions on Computers

Drechsler, R.

https://doi.org/10.1109/12.795226

1999 // Conference paper

SBDD variable reordering based on probabilistic and evolutionary algorithms

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Thornton, M.A.; Williams, J.P.; Drechsler, R.; Drechsler, N.; Wessels, D.M.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0033342847&partnerID=MN8TOARS

1999 // Conference paper

Synthesis of Pseudo-Kronecker Lattice Diagrams

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Lindgren, Per; Drechsler, Rolf; Becker, Bernd

http://www.scopus.com/inward/record.url?eid=2-s2.0-0033300432&partnerID=MN8TOARS

1999 // Journal article

Testability of 2-level AND/EXOR circuits

Journal of Electronic Testing: Theory and Applications (JETTA)

Drechsler, R.; Hengster, H.; Schäfer, H.; Hartmann, J.; Becker, B.

https://doi.org/10.1023/A:1008306002882

1999 // Conference paper

Using Lower Bounds During Dynamic BDD Minimization

Proceedings - Design Automation Conference

Drechsler, Rolf; Guenther, Wolfgang

http://www.scopus.com/inward/record.url?eid=2-s2.0-0032638517&partnerID=MN8TOARS

1999 // Conference paper

Variable reordering for shared binary decision diagrams using output probabilities

Proceedings -Design, Automation and Test in Europe, DATE

Thornton, M.A.; Williams, J.P.; Drechsler, R.; Drechsler, N.

https://doi.org/10.1109/DATE.1999.761217

1998 // Journal article

Complexity of the inclusion operation on OFDDs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Drechsler, Rolf; Sauerhoff, Martin; Sieling, Detlef

https://doi.org/10.1109/43.703943

1998 // Conference paper

Dual-edge operations in reduced-order binary decision diagrams

Proceedings - IEEE International Symposium on Circuits and Systems

Miller, D.M.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031619193&partnerID=MN8TOARS

1998 // Conference paper

Dynamic Minimization of Word-Level Decision Diagrams

Proceedings -Design, Automation and Test in Europe, DATE

Höreth, S.; Drechsler, R.

https://doi.org/10.1109/DATE.1998.655921

1998 // Conference paper

ETDD-based synthesis of term-based FPGAs for incompletely specified Boolean functions

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Lee, Gueesang; Drechsler, Rolf

http://www.scopus.com/inward/record.url?eid=2-s2.0-0032218707&partnerID=MN8TOARS

1998 // Conference paper

Nearly Exact Minimization of BDDs

Proceedings - Design Automation Conference

Drechsler, Rolf; Drechsler, Nicole; Guenther, Wolfgang

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031624147&partnerID=MN8TOARS

1998 // Conference paper

Implementing a multiple-valued decision diagram package

Proceedings of The International Symposium on Multiple-Valued Logic

Miller, D. Michael; Drechsler, Rolf

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031633112&partnerID=MN8TOARS

1998 // Conference paper

Improved Minimization Methods for Pseudo-Kronecker Expressions with Multiple Output Functions

Proceedings - IEEE International Symposium on Circuits and Systems

Lindgren, Per; Drechsler, Rolf; Becker, Bernd

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031642077&partnerID=MN8TOARS

1998 // Conference paper

Linear Transformations and Exact Minimization of BDDs

Proceedings of the IEEE Great Lakes Symposium on VLSI

Guenther, Wolfgang; Drechsler, Rolf

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031653175&partnerID=MN8TOARS

1998 // Conference paper

Look-up Table FPGA Synthesis from Minimized Multi-valued Pseudo-Kronecker Expressions

Proceedings of The International Symposium on Multiple-Valued Logic

Lindgren, Per; Drechsler, Rolf; Becker, Bernd

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031637075&partnerID=MN8TOARS

1998 // Conference paper

Manipulation of *BMDs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Drechsler, Rolf; Hoereth, Stefan

http://www.scopus.com/inward/record.url?eid=2-s2.0-0032218634&partnerID=MN8TOARS

1998 // Journal article

On Variable Ordering and the Choice of Decomposition Type in OKFDDs

IEEE Transactions on Computers

Drechsler, R.; Becker, B.; Jahnke, A.

https://doi.org/10.1109/12.737685

1998 // Journal article

Ordered Kronecker Functional Decision Diagrams—A Data Structure for Representing and Manipulating Boolean Functions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Drechsler, R.; Becker, B.

https://doi.org/10.1109/43.728917

1998 // Conference paper

Test Generation for (Sequential) Multi-valued Logic Networks Based on a Genetic Algorithm

Proceedings of The International Symposium on Multiple-Valued Logic

Keim, Martin; Drechsler, Nicole; Drechsler, Rolf; Becker, Bernd

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031619677&partnerID=MN8TOARS

1998 // Book

Verifying the Integrity of Decision Diagrams

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84889050821&partnerID=MN8TOARS

1997 // Conference paper

(Quasi-)linear path delay fault tests for adders

Proceedings of the IEEE International Conference on VLSI Design

Becker, B.; Drechsler, R.; Reddy, S.M.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0030734605&partnerID=MN8TOARS

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Prof. Rolf Drechsler

Ecosystem

Publications

Multi-objective Optimization in Evolutionary Algorithms Using Satisfiability Classes

OKFDD Minimization Using Genetic Algorithms with Application to Circuit Design

Power Consumption in XOR-Based Circuits

Probabilistic IP Verification

Pseudo-Kronecker Expressions for Symmetric Functions

SBDD variable reordering based on probabilistic and evolutionary algorithms

Synthesis of Pseudo-Kronecker Lattice Diagrams

Testability of 2-level AND/EXOR circuits

Using Lower Bounds During Dynamic BDD Minimization

Variable reordering for shared binary decision diagrams using output probabilities

Complexity of the inclusion operation on OFDDs

Dual-edge operations in reduced-order binary decision diagrams

Dynamic Minimization of Word-Level Decision Diagrams

ETDD-based synthesis of term-based FPGAs for incompletely specified Boolean functions

Nearly Exact Minimization of BDDs

Implementing a multiple-valued decision diagram package

Improved Minimization Methods for Pseudo-Kronecker Expressions with Multiple Output Functions

Linear Transformations and Exact Minimization of BDDs

Look-up Table FPGA Synthesis from Minimized Multi-valued Pseudo-Kronecker Expressions

Manipulation of *BMDs

On Variable Ordering and the Choice of Decomposition Type in OKFDDs

Ordered Kronecker Functional Decision Diagrams—A Data Structure for Representing and Manipulating Boolean Functions

Test Generation for (Sequential) Multi-valued Logic Networks Based on a Genetic Algorithm

Verifying the Integrity of Decision Diagrams

(Quasi-)linear path delay fault tests for adders

Please feel free to mail us, if you have any further questions

Please feel free to mail us, if you have any further questions