Wissenschaftsschwerpunkt der

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© Jörg Sarbach
© Jörg Sarbach
Prof. Rolf Drechsler
  • Fachbereich: Fachbereich 3 - Mathematik & Informatik
  • Fachgebiet: Computer Architecture (systems descriptions, test and verification, synthesis) Further Information: Group of Computer Architecture; Group of Reliable Embedded Systems; DFKI Cyber Physical Systems
  • Büro: MZH 4330

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Mitglied des Direktoriums des Wissenschaftsschwerpunkts "Minds, Media, Machines"
Leiter der Arbeitsgruppe Rechnerarchitektur
Direktor der Gruppe Cyber Physical Systems am Deutschen Forschungszentrum für Künstliche Intelligenz (DFKI)
Mitgründer und Sprecher des Data Science Center (DSC) an der Universität Bremen
Dekan des Fachbereichs 3 Mathematik/Informatik
Betreuer für das Graduiertenkolleg „CAUSE“
Mitglied des CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI
Mitglied des Direktoriums des Forschungscluster "Logdynamics"
Publikationen
1999 // Book

Multi-objective optimization in evolutionary algorithms using satisfiability classes

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, N.; Drechsler, R.; Becker, B.
http://www.scopus.com/inward/record.url?eid=2-s2.0-84937399878&partnerID=MN8TOARS
1999 // Journal article

OKFDD minimization by genetic algorithms with application to circuit design

Integration, the VLSI Journal

Drechsler, R.; Becker, B.; Drechsler, N.
https://doi.org/10.1016/S0167-9260(99)00017-6
1999 // Conference paper

Power consumption in XOR-based circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Kaushik Roy, Y.Y.; Drechsler, R.
https://doi.org/10.1109/ASPDAC.1999.760018
1999 // Conference paper

Probabilistic IP verification

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Drechsler, Rolf; Becker, Bernd
http://www.scopus.com/inward/record.url?eid=2-s2.0-0033327304&partnerID=MN8TOARS
1999 // Journal article

Pseudo-Kronecker Expressions for symmetric functions

IEEE Transactions on Computers

Drechsler, R.
https://doi.org/10.1109/12.795226
1999 // Conference paper

SBDD variable reordering based on probabilistic and evolutionary algorithms

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Thornton, M.A.; Williams, J.P.; Drechsler, R.; Drechsler, N.; Wessels, D.M.
http://www.scopus.com/inward/record.url?eid=2-s2.0-0033342847&partnerID=MN8TOARS
1999 // Conference paper

Synthesis of pseudo Kronecker lattice diagrams

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Lindgren, Per; Drechsler, Rolf; Becker, Bernd
http://www.scopus.com/inward/record.url?eid=2-s2.0-0033300432&partnerID=MN8TOARS
1999 // Journal article

Testability of 2-level AND/EXOR circuits

Journal of Electronic Testing: Theory and Applications (JETTA)

Drechsler, R.; Hengster, H.; Schäfer, H.; Hartmann, J.; Becker, B.
https://doi.org/10.1023/A:1008306002882
1999 // Conference paper

Using lower bounds during dynamic BDD minimization

Proceedings - Design Automation Conference

Drechsler, Rolf; Guenther, Wolfgang
http://www.scopus.com/inward/record.url?eid=2-s2.0-0032638517&partnerID=MN8TOARS
1999 // Conference paper

Variable reordering for shared binary decision diagrams using output probabilities

Proceedings -Design, Automation and Test in Europe, DATE

Thornton, M.A.; Williams, J.P.; Drechsler, R.; Drechsler, N.
https://doi.org/10.1109/DATE.1999.761217
1998 // Journal article

Complexity of the inclusion operation on OFDD's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Drechsler, Rolf; Sauerhoff, Martin; Sieling, Detlef
https://doi.org/10.1109/43.703943
1998 // Conference paper

Dual edge operations in reduced ordered binary decision diagrams

Proceedings - IEEE International Symposium on Circuits and Systems

Miller, D.M.; Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-0031619193&partnerID=MN8TOARS
1998 // Conference paper

Dynamic minimization of word-level decision diagrams

Proceedings -Design, Automation and Test in Europe, DATE

Höreth, S.; Drechsler, R.
https://doi.org/10.1109/DATE.1998.655921
1998 // Conference paper

ETDD-based synthesis of term-based FPGAs for incompletely specified Boolean functions

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Lee, Gueesang; Drechsler, Rolf
http://www.scopus.com/inward/record.url?eid=2-s2.0-0032218707&partnerID=MN8TOARS
1998 // Conference paper

Fast exact minimization of BDDs

Proceedings - Design Automation Conference

Drechsler, Rolf; Drechsler, Nicole; Guenther, Wolfgang
http://www.scopus.com/inward/record.url?eid=2-s2.0-0031624147&partnerID=MN8TOARS
1998 // Conference paper

Implementing a multiple-valued decision diagram package

Proceedings of The International Symposium on Multiple-Valued Logic

Miller, D.Michael; Drechsler, Rolf
http://www.scopus.com/inward/record.url?eid=2-s2.0-0031633112&partnerID=MN8TOARS
1998 // Conference paper

Improved minimization methods of Pseudo Kronecker Expressions for multiple output functions

Proceedings - IEEE International Symposium on Circuits and Systems

Lindgren, Per; Drechsler, Rolf; Becker, Bernd
http://www.scopus.com/inward/record.url?eid=2-s2.0-0031642077&partnerID=MN8TOARS
1998 // Conference paper

Linear transformations and exact minimization of BDDs

Proceedings of the IEEE Great Lakes Symposium on VLSI

Guenther, Wolfgang; Drechsler, Rolf
http://www.scopus.com/inward/record.url?eid=2-s2.0-0031653175&partnerID=MN8TOARS
1998 // Conference paper

Look-up Table FPGA synthesis from minimized multi-valued pseudo kronecker expressions

Proceedings of The International Symposium on Multiple-Valued Logic

Lindgren, Per; Drechsler, Rolf; Becker, Bernd
http://www.scopus.com/inward/record.url?eid=2-s2.0-0031637075&partnerID=MN8TOARS
1998 // Conference paper

Manipulation of *BMDs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Drechsler, Rolf; Hoereth, Stefan
http://www.scopus.com/inward/record.url?eid=2-s2.0-0032218634&partnerID=MN8TOARS
1998 // Journal article

On variable ordering and decomposition type choice in OKFDDs

IEEE Transactions on Computers

Drechsler, R.; Becker, B.; Jahnke, A.
https://doi.org/10.1109/12.737685
1998 // Journal article

Ordered kronecker functional decision diagrams - A data structure for representation and manipulation of boolean functions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Drechsler, R.; Becker, B.
https://doi.org/10.1109/43.728917
1998 // Conference paper

Test generation for (sequential) multi-valued logic networks based on genetic algorithm

Proceedings of The International Symposium on Multiple-Valued Logic

Keim, Martin; Drechsler, Nicole; Drechsler, Rolf; Becker, Bernd
http://www.scopus.com/inward/record.url?eid=2-s2.0-0031619677&partnerID=MN8TOARS
1998 // Book

Verifying integrity of decision diagrams

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, R.
http://www.scopus.com/inward/record.url?eid=2-s2.0-84889050821&partnerID=MN8TOARS
1997 // Conference paper

(Quasi-) linear path delay fault tests for adders

Proceedings of the IEEE International Conference on VLSI Design

Becker, B.; Drechsler, R.; Reddy, S.M.
http://www.scopus.com/inward/record.url?eid=2-s2.0-0030734605&partnerID=MN8TOARS

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.

mmm@uni-bremen.de 

  • 2026 Minds, Media, Machines

Schreiben Sie uns gerne eine E-Mail, falls Sie weitere Fragen haben.

mmm@uni-bremen.de 

  • 2026 Minds, Media, Machines