Prof. Rolf Drechsler

Weitere Informationen:

AG Rechnerarchitektur & Zuverlässige Eingebettete Systeme; DFKI Cyber Physical Systems

Ökosystem

Mitglied des Direktoriums des Wissenschaftsschwerpunkts "Minds, Media, Machines"

Leiter der Arbeitsgruppe Rechnerarchitektur

Direktor der Gruppe Cyber Physical Systems am Deutschen Forschungszentrum für Künstliche Intelligenz (DFKI)

Mitgründer und Sprecher des Data Science Center (DSC) an der Universität Bremen

Dekan des Fachbereichs 3 Mathematik/Informatik

Betreuer für das Graduiertenkolleg „CAUSE“

Mitglied des CoAI JRC Joint Research Center on Cooperative and Cognition enabled AI

Mitglied des Direktoriums des Forschungscluster "Logdynamics"

Publikationen

2001 // Journal article

Combining GAs and symbolic methods for high quality tests of sequential circuits

Journal of Electronic Testing: Theory and Applications (JETTA)

Keim, M.; Drechsler, N.; Drechsler, R.; Becker, B.

https://doi.org/10.1023/A:1011193725824

2001 // Journal article

Decision diagram method for calculation of pruned Walsh transform

IEEE Transactions on Computers

Jankovic, D.; Stankovic, R.S.; Drechsler, R.

https://doi.org/10.1109/12.908990

2001 // Journal article

Equivalence checking of digital circuits in an industrial environment,Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld

IT - Information Technology

Drechsler, R.

https://doi.org/10.1524/itit.2001.43.4.200

2001 // Conference paper

Evolutionary algorithm approach for symbolic FSM traversals

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings

Thornton, M.A.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0034770456&partnerID=MN8TOARS

2001 // Conference paper

GREEDY IIP: Partitioning large graphs by greedy iterative improvement

Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Becker, B.; Drechsler, R.; Eschbach, T.; Gunther, W.

https://doi.org/10.1109/DSD.2001.952117

2001 // Book

Heuristic learning based on genetic programming

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, N.; Schmiedle, F.; Gro e, D.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0037908000&partnerID=MN8TOARS

2001 // Journal article

History-based dynamic BDD minimization

Integration, the VLSI Journal

Drechsler, R.; Günther, W.

https://doi.org/10.1016/S0167-9260(01)00021-9

2001 // Conference paper

Implementation of read-κ-times BDDs on top of standard BDD packages

Proceedings of the IEEE International Conference on VLSI Design

Günther, W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0035013771&partnerID=MN8TOARS

2001 // Conference paper

Level assignment for displaying combinational logic

Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Drechsler, R.; Günther, W.; Linhard, L.; Angst, G.

https://doi.org/10.1109/DSD.2001.952262

2001 // Conference paper

Low power optimization technique for BDD mapped circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Lindgren, P.; Kerttu, M.; Thornton, M.; Drechsler, R.

https://doi.org/10.1109/ASPDAC.2001.913377

2001 // Conference paper

Minimization of OPKFDDs using genetic algorithms

Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Jung, M.; Lee, G.; Park, S.; Drechsler, R.

https://doi.org/10.1109/DSD.2001.952120

2001 // Book

Multi-objective optimisation based on relation favour

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Drechsler, N.; Drechsler, R.; Becker, B.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84931462371&partnerID=MN8TOARS

2001 // Conference paper

Performance driven optimization for MUX based FPGAs

Proceedings of the IEEE International Conference on VLSI Design

Günther, W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0034998852&partnerID=MN8TOARS

2001 // Conference paper

Selection of efficient re-ordering heuristics for MDD construction

Proceedings of The International Symposium on Multiple-Valued Logic

Schmiedle, F.; Günther, W.; Drechsler, R.

http://www.scopus.com/inward/record.url?eid=2-s2.0-0034829963&partnerID=MN8TOARS

2001 // Conference paper

Spectral decision diagrams using graph transformations

Proceedings -Design, Automation and Test in Europe, DATE

Thornton, M.; Drechsler, R.

https://doi.org/10.1109/DATE.2001.915106

2001 // Book

Too much knowledge hurts: Acceleration of genetic programs for learning heuristics

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Schmiedle, F.; Große, D.; Drechsler, R.; Becker, B.

http://www.scopus.com/inward/record.url?eid=2-s2.0-84883817522&partnerID=MN8TOARS

2001 // Journal article

Using lower bounds during dynamic BDD minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Drechsler, R.; Günther, W.; Somenzi, F.

https://doi.org/10.1109/43.905674

2000 // Conference paper

ACTion: Combining logic synthesis and technology mapping for MUX based FPGAs

Conference Proceedings of the EUROMICRO

Günther, W.; Drechsler, R.

https://doi.org/10.1109/EURMIC.2000.874625

2000 // Journal article

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

Journal of Systems Architecture

Günther, W.; Drechsler, R.

https://doi.org/10.1016/S1383-7621(00)00027-8

2000 // Journal article

Boolean function representation and spectral characterization using AND/OR graphs

Integration, the VLSI Journal

Žužek, A.; Drechsler, R.; Thornton, M.A.

https://doi.org/10.1016/S0167-9260(00)00003-1

2000 // Journal article

Computation of spectral information from logic netlists

Proceedings of The International Symposium on Multiple-Valued Logic

Drechsler, R.; Thornton, M.

https://doi.org/10.1109/ISMVL.2000.848600

2000 // Conference paper

Design reuse by modularity: A scalable dynamical (re)configurable multiprocessor system

Conference Proceedings of the EUROMICRO

Drechsler, R.; Drechsler, N.; Mackensen, E.; Schubert, T.; Becker, B.

https://doi.org/10.1109/EURMIC.2000.874662

2000 // Conference paper

Dynamic re-encoding during MDD minimization

Proceedings of The International Symposium on Multiple-Valued Logic

Schmiedle, Frank; Guenther, Wolfgang; Drechsler, Rolf

http://www.scopus.com/inward/record.url?eid=2-s2.0-0033691931&partnerID=MN8TOARS

2000 // Conference paper

Efficient dynamic minimization of Word-Level DDs based on lower bound computation

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Guenther, Wolfgang; Drechsler, Rolf; Hoereth, Stefan

http://www.scopus.com/inward/record.url?eid=2-s2.0-0033711556&partnerID=MN8TOARS

2000 // Journal article

ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions

IEE Proceedings: Computers and Digital Techniques

Lee, G.; Drechsler, R.; Perkowski, M.A.

https://doi.org/10.1049/ip-cdt:19990798

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Prof. Rolf Drechsler

Ökosystem

Publikationen

Combining GAs and symbolic methods for high quality tests of sequential circuits

Decision diagram method for calculation of pruned Walsh transform

Equivalence checking of digital circuits in an industrial environment,Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld

Evolutionary algorithm approach for symbolic FSM traversals

GREEDY IIP: Partitioning large graphs by greedy iterative improvement

Heuristic learning based on genetic programming

History-based dynamic BDD minimization

Implementation of read-κ-times BDDs on top of standard BDD packages

Level assignment for displaying combinational logic

Low power optimization technique for BDD mapped circuits

Minimization of OPKFDDs using genetic algorithms

Multi-objective optimisation based on relation favour

Performance driven optimization for MUX based FPGAs

Selection of efficient re-ordering heuristics for MDD construction

Spectral decision diagrams using graph transformations

Too much knowledge hurts: Acceleration of genetic programs for learning heuristics

Using lower bounds during dynamic BDD minimization

ACTion: Combining logic synthesis and technology mapping for MUX based FPGAs

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs

Boolean function representation and spectral characterization using AND/OR graphs

Computation of spectral information from logic netlists

Design reuse by modularity: A scalable dynamical (re)configurable multiprocessor system

Dynamic re-encoding during MDD minimization

Efficient dynamic minimization of Word-Level DDs based on lower bound computation

ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions

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